From: Adam Krolnik (adamk@cyrix.com)
Date: Mon May 11 1998 - 23:43:08 PDT
Eli wrote:
>It may be late but here is another request for Verilog extension. I
>would like to add the directive `file. E.g.
>`file myfile 156
Just to note, cpp encodes this information in a different format:
#line integer-constant "filename"
Maybe we should keep the same format and have this directive:
`line integer "filename"
On the subject of preprocessor directives, things missing from the
verilog preprocessor that are present in cpp include:
#if - check value - not existance if definition
#elif - else if chain (removes endif endif endif...)
Maybe we should include the last three directives missing for completeness.
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM.
Richardson TX. 75085
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