From: Stuart Sutherland (stuart@sutherland.com)
Date: Thu May 21 1998 - 00:07:44 PDT
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Here's a thought on this issue from the PLI task force...
In section 3.8 of the 1995 LRM, "memories" are specifically defined as an
array of "reg" registers. The next section, in the middle of page 24,
implies, but does clearly state, that an array of integers and time
registers is not the same as a "memory". The PLI standard makes a definite
distinction between a variable array and a memory array (sections 22.5.6
and 22.5.7).
Even though and array of reg and an array of integer/time registers are
declared the same way, I think it is important to maintain the wording
Verilog modelers are familiar with. I suggest that the proposed 1998 LRM
should:
a) Create a new section before 3.9, describing the intent and behavior of
"reg".
b) Keep section 3.9, which describes the intent and behavior of "integer",
"time" "real" and "realtime", but delete the single sentence paragraph
beginning with "Arrays of integer and time..."
c) Create a new section after 3.9, describing arrays of reg, integer, and
time.
d) Move section 3.8 on "Memories" to after the definition of arrays, and
simplify the section to state that a memory is a just special name for a
1-demisional array of "reg" registers, which can be used to represent the
storage of a RAM or ROM. Example 1 of 3.8 should stay with description of
memories.
Keeping the definition of a "memory" in section 3 is important! It will
help us on the PLI task force keep the PLI terminology that Verilog users
are familiar with. It will also help us document that the older TF
routines in the PLI can only access "memory" arrays, whereas the VPI
routines will be able to access multi-dimensional arrays of any type.
Stu
At 04:48 PM 5/20/98 +0300, Shalom Bresticker wrote:
>1. This proposal talks about "memories" and "multi-dimensional arrays" as
though
>they were two different types of entities.
>
>I don't see any difference between them.
>(Originally memories were limited to reg's, but this proposal removes that
>limitation.)
>
>The original Verilog called these memories because the original intention
>was to enable modeling of memories, and the syntax allowed only
two-dimensional
>arrays, just enough to allow modeling of memories, but "memory" was never a
>keyword of Verilog, as "reg" or "wire" is, just a term used to denote a two-
>dimensional array.
>
>I propose just calling them "arrays", without even the "multi-dimensional".
>It is a simple and clear term.
>
>The first paragraph of 3.8 should make clear that memories and connections of
>generated instances are only examples of uses of arrays.
>
>
>2. The end of this proposal says that "Bit and part selects of
multi-dimensional
>arrays cannot be expressed because the elements are single bits.", whereas
bit
>selects and part selects of memories are allowed a few lines earlier.
>
>This sounds like a mistake. First, I see no syntactic difference between
memories
>and multi-dimensional arrays.
>
>Furthermore, B26 explicitly allows bit and part selects to arrays.
>
>***************************************************************************
***
>Shalom Bresticker email: shalom@msil.sps.mot.com
>Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
>P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
>http://www.motorola-semi.co.il/
>***************************************************************************
***
>
>
>> Date: Tue, 19 May 1998 12:46:41 -0700
>> From: Stefen Boyd <stefen@boyd.com>
>> Subject: B02 and B26 draft
>>
>> I've taken a stab at B02 and B26. I expect there is some more
>> polishing to do here...
>
>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland.com
Specializing in Verilog HDL consulting and training. Publisher of the
popular Verilog HDL and Verilog PLI quick reference guides.
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