From: Adam Krolnik (adamk@cyrix.com)
Date: Fri May 22 1998 - 04:03:07 PDT
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE71
Errata Name (Description): Section 5.6.6 Port connections
Section: 5.6.6
Date Submitted: 980313
Requestor: Adam Krolnik
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Section 5.6.6 "Port connections" describes the seldom seen syntax for specifying a port with separate internal and external names.
Why is this text in this section? Why is there no reference to 5.6.6 and this available
syntax in section 12.3?
I propose that this orphan port syntax description be moved to it's correct location (section 12.3). I.e. The Third paragraph should only read "Port connection rules are given in 12.3.7."
[And possibly should be joined to the first paragraph.]
Section 12.3 should include an example of a module with this specific syntax and an example
of it being instantiated.
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM.
Richardson TX. 75085
<p>[Note: I have taken the liberty to include Shalom Bresticker's proposals on
inaccuracies of section 12 and add my comments.]
Proposal (Section 5.6.6):
1. Remove the 3rd paragraph (stars with "Port connection rules are") and the rest
of the text in section 5.6.6
Proposal (Section 12.1, 12.2, 12.3)
1. Recommend reorder of sections 12.1.2, 12.2 and 12.3 to describe ports of a module
before instantiation, port connections and parameter overriding. It seems strange to
be shown how to instantiate a module without knowing how to define ports to it.
Also, there is the statement "See 12.3 for the definition of ports." at the end
of section 12[.0]; why not put the port section next instead of making a forward
reference.
12.2 Ports.
12.2.1 Port definition.
12.2.2 Port declarations.
12.3 Module instantiation.
12.3.1 Connecting module ports by ordered list.
12.3.2 Connecting module ports by name.
12.3.3 Real numbers in port connections.
12.3.4 Connecting dissimilar ports.
12.3.5 Port connection rules
12.3.5.1 Rule1
12.3.5.2 Rule2
12.3.6 Net types resulting from dissimilar port connections.
12.3.6.1 Net type resolution rule
12.3.6.2 Net type table
12.4 Overriding module parameter values.
12.4.1 Defparam statement.
12.4.2 Module instance parameter value assignment.
12.4.3 Parameter dependence.
2. Recommend change name of 'list_of_module_connections' to 'list_of_port_connections"
as it is more consistent with 'list_of_ports' and the section refers to "port
connections" rather than module connections. (Shalom)
3. Add definition of 'named_port_connection' to Syntax box 12-2 (Shalom)
It is currently missing from the box.
4. Alter 3rd paragraph after the syntax box to (addition is in []):
"The list of module connections shall be provided only for modules defined
with ports. The parenthesis, however, are always required. When a list of
module connections is given [using the ordered port connection method],
the first element in the list shall connect to the first port [declared
in the module], the second to the second port, and so on. See section 12.3
for a more detailed discussion of ports and port connection rules."
5. Strike the parenthetical statement in 12.3.1 "(this is the completion of the
syntax presented in 12.1)". Syntax box 12-3 is contained in syntax box 12-1! (Shalom)
6. Strike the sentence in section 12.3.1 last paragraph, "The two types of
module port definitions shall not be mixed; the ports of a particular
module definition shall all be defined by order or all by name." This is
for port connections, not declarations in the module. The simulators allow
mixture of methods as does the BNF. (Shalom)
7. Replace the first, second paragraphs and following list of section 12.3.4
"Connecting module ports by name" with this paragraph. (Shalom and Adam)
"The second way to connect module ports explicitly specifies the port name,
as listed in the module definition. This method cannot be used for names
defined in the module as a bit-select, part-select, or concatenation of ports.
The current text ("explicitly linking two names") is unclear because an
expression may be used in a port connection instead of a net name; The
list describing the port expression is incorrect - an expression is
not listed, nor is a null expression.
8. Add some examples for section 12.3.1, E.g.
module simple_ports( a, b, c); -- Names 'a', 'b' and 'c' are defined inside module.
module complex_ports ({c,d}, .e(f)); -- Nets {c,d} receive the first port bits.
Name 'f' is defined inside the module.
Name 'e' is defined outside the module.
Can't use named port connections because
of first port.
module split_ports (a[7:4], a[3:0]); First port is upper 4 bits of 'a'.
Second port is lower 4 bits of 'a'.
Can't use named port connections because
of part-select port 'a'.
module same_port (.a(i), .b(i)); Name 'i' is defined inside the module as
a inout port. Names 'a' and 'b' are
defined for port connections.
module renamed_concat (.a({b,c}), f, Names 'b', 'c', 'f', 'h' are defined
.g(h[1])); inside the module.
Names 'a', 'f', 'g' are defined for
port connections.
Can use named port connections.
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM.
Richardson TX. 75085
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