From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Sun May 24 1998 - 00:42:15 PDT
BAD MSG:
I accept Stuart's claim that the PLI standard requires definition of "memory" as
special type of arrays.
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I also accept his suggestions as to how to re-organize 3.8 and 3.9, with a few
small comments:
1. What Stuart proposes, to 'create a new section before 3.9, describing the intent
and behavior of "reg"', basically already exists in 3.2.2.
2. The current wording of B02, while at the beginning, says that arrays can be of
regs or nets, later reverts to the assumption that arrays are regs. An example is in
the beginning of the 2nd paragraph, which talks about "register declaration
statements".
3. What about real and realtime? Are there arrays of these also?
Sincerely,
******************************************************************************
Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
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> From stuart@sutherland.com Thu May 21 17:27:10 1998
> From: Stuart Sutherland <stuart@sutherland.com>
> Subject: Re: B02 and B26 draft
>
>
> Here's a thought on this issue from the PLI task force...
>
> In section 3.8 of the 1995 LRM, "memories" are specifically defined as an
> array of "reg" registers. The next section, in the middle of page 24,
> implies, but does clearly state, that an array of integers and time
> registers is not the same as a "memory". The PLI standard makes a definite
> distinction between a variable array and a memory array (sections 22.5.6
> and 22.5.7).
>
> Even though and array of reg and an array of integer/time registers are
> declared the same way, I think it is important to maintain the wording
> Verilog modelers are familiar with. I suggest that the proposed 1998 LRM should:
>
> a) Create a new section before 3.9, describing the intent and behavior of "reg".
>
> b) Keep section 3.9, which describes the intent and behavior of "integer",
> "time" "real" and "realtime", but delete the single sentence paragraph
> beginning with "Arrays of integer and time..."
>
> c) Create a new section after 3.9, describing arrays of reg, integer, and time.
>
> d) Move section 3.8 on "Memories" to after the definition of arrays, and
> simplify the section to state that a memory is a just special name for a
> 1-dimensional array of "reg" registers, which can be used to represent the
> storage of a RAM or ROM. Example 1 of 3.8 should stay with description of
> memories.
>
> Keeping the definition of a "memory" in section 3 is important! It will
> help us on the PLI task force keep the PLI terminology that Verilog users
> are familiar with. It will also help us document that the older TF
> routines in the PLI can only access "memory" arrays, whereas the VPI
> routines will be able to access multi-dimensional arrays of any type.
>
> Stu
>
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