B02 and B26 draft - take 2

From: Stefen Boyd (stefen@boyd.com)
Date: Tue May 26 1998 - 11:47:55 PDT

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BAD MSG:
I've incorporated the various comments. I've tried to
aintain the concept of a memory for the sake of the
pli folks, but make it clearer that it's just a special
case of a one dim reg arrays.
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I could really use some better wording for section
3.8 registers. If one of you would like to contribute
something from your verilog class material that is
more presentable, please do so.

Thanks,
Stefen

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B02: Multi-Dimensional Arrays
 
changes are marked in red
 B26: bit selects of elements in arrayed structures
 changes
are marked in blue
 Proposal

Add Clif's changed bnf to syntax boxes 3-1 and 3-2.

Change Section 3.8 (memories get moved into new section
3.10):

3.8 Registers

A reg models hardware registers.
Assignments to a reg are made by procedural assignments (See sections 6.2
and 9.2). Since the reg holds a value between assignments, it can
be used to model hardware registers. Edge-sensitive (i.e. flip-flops)
and level sensitive (i.e. RS and transparent latches) storage elements
can be modeled. A reg need not represent a hardware storage element
since it can also be used to represent combinatorial logic.

Change section 3.9
 Update bnf with Clif's modified version
 Strike paragraph:
 <STRIKE>Arrays of integer
and time registers shall be declared in the same manner as arrays of reg
type (section 3.8).</STRIKE>
 change examples:
 
integer a;
// integer value
 
time last_chng;
// time value
 <STRIKE>
integer a[1:64];
// an array of 64 integer values</STRIKE>
 <STRIKE>
time chng_hist[1:1000] // an array of 1000 time values</STRIKE>

Add new section 3.10 (push parameters down one section)

3.10 Arrays

Arrays can be used to group
elements of net and reg types. They shall be declared in net and
register declaration statements by specifying the element address range(s)
after the declared identifier. Each dimension shall be represented by an
address range. See sections 3.2.1 and 3.2.2 for net and register
declarations. The expression(s) that specify the indices of the array shall
be constant expressions. The value of the constant expression can be a
positive integer, a negative integer, or zero.

One declaration statement can
be used for declaring both nets or registers and arrays. This makes it
convenient to declare both an array and some nets or registers that will
match the element vector width in the same declaration statement.

An n-bit register or net can
be assigned a value in a single assignment, but a complete or partial array
dimension cannot. Nor can a complete or partial array dimension be used
to provide a value to an expression. To assign a value to an element,
an index for every dimension shall be specified. The index can be an expression.
This option provides a mechanism to reference different array elements
depending on the value of other registers and nets in the circuit. For
example, a program counter register could be used to index into a RAM.

3.10.1 Net Arrays

Arrays of nets can be used
to connect ports of generated instances. Each element of the array
can be used in the same fashion as a scalar or vector net.

3.10.2 Register Arrays
 Arrays for all register types
(reg, integer, time, real, realtime) shall be possible.

Examples:

3.<STRIKE>8</STRIKE>10.3
Memories

A<STRIKE>n</STRIKE>
one dimensional array of registers can be
used to model read-only memories (ROMs), random access memories (RAMs),
and register files. Each register in the array is known as an element or
word and is addressed by a single array index. <STRIKE>There
shall be no arrays with multiple dimensions.</STRIKE>

<STRIKE>Memories shall be declared
in register</STRIKE>...

<STRIKE>One declaration statement
can be used for declaring registers and memories. This makes it convenient
to declare both a memory and some registers that will hold data to be read
from and written to the memory in the same declaration statement.</STRIKE>

3.10.4 Array Examples

1. <STRIKE>Memory</STRIKE>Array
declarations
<OL>reg [7:0] mema[0:255]; // declare
a memory mema of 256 eight-bit
 
// eight-bit registers. The indeces are 0 to 255
 reg arrayb[7:0][0:255];
// declare a two dimentional array of one bit
 
// registers
 wire w_array[7:0][5:0];
// declare array of wires
 integer inta[1:64];
// an array of 64 integer values
 time chng_hist[1:1000]
// an array of 1000 time values
 integer t_index;</OL>
2. A memory of n 1-bit registers is different from an
n-bit vector register (no changes)

3. Assignment to <STRIKE>memory
</STRIKE>array elements
<DIR>
<DIR>rega = 0; // Legal Syntax
 mema = 0; // Illegal Syntax
 arrayb[1] = 0; // Illegal
Syntax
 mema[1] = 0; // Assigns 0 to the <STRIKE>first</STRIKE>
second element of mema
 arrayb[1][0] = 0; // Assigns
0 to the bit referenced by indices [1][0]
 inta[4] = 33559; //
Assign decimal number to integer in array
 chng_hist[t_index] = $time;
// Assign current simulation time to element addressed
 
// by integer index</DIR>
</DIR>
Section 4: Change next to last line of "An
operand can be one of the following:"

-- <STRIKE>memory</STRIKE>
array element

Section 4.2.2:

4.2.2 Array
and Memory addressing
 Declarations of arrays
and memor<STRIKE>y</STRIKE>ies
(one dimensional arrays of reg) <STRIKE>is</STRIKE> are discussed
in section 3.<STRIKE>8</STRIKE>10. This
section discusses array <STRIKE>memory</STRIKE>
addressing.

Example
 The next example declares a memory of
1024 8-bit words:

reg [7:0] mem_name[0:1023];

The syntax for a memory address shall consist
of the name of the memory and an expression for the address - specified
with the following format:

mem_name[addr_expr]

The addr_expr can be any expression; therefore,
memory indirections can be specified in a single expression. Additional
The next example illustrates memory indirection:
 
 mem_name[mem_name[3]]

In the above example, mem_name[3] addresses
word three of the memory called mem_name. The value at word three
is the index into mem_name that is used by the memory address mem_name[mem_name[3]].
As with bit-selects, the address bounds given in the declaration of the
memory determine the effect of the address expression. If the index
is out of the address bounds or if any bit in the address is x or z, then
the value of the reference shall be x.

Example
 The next example
declares an array of 256 by 256 8-bit elements and an array 256 by 256
by 8 1-bit elements:

reg [7:0] twod_array[0:255][0:255];
 
wire threed_array[0:255][0:255][0:7];

The syntax for access
to the array shall consist of the name of the memory or array and an expression
for each addressed dimension:
 
twod_array[addr_expr][addr_expr]
 
threed_array[addr_expr][addr_expr][addr_expr]

As before, the addr_expr
can be any expression. The array twod_array accesses a whole 8-bit
vector, while the array threed_array accesses a single bit of the three
dimensional array.

To express bit selects
or part selects of array elements, the desired word shall first be selected
by supplying an address for each dimension. Once selected, bit and
part selects shall be addressed in the same manner as net and register
bit and part selects (Section 4.2.1).

Examples
 
twod_mem[14][1][3:0] // access lower
4 bits of word
 
twod_mem[1][3][6]
// access bit 6 of word
 
twod_mem[1][3][sel] //
use variable bit select
 
threed_array[14][1][3:0] // Illegal

<STRIKE>NOTE - There
is no mechanism to express bit-selects or part-selects of memory elements
directly. If this is required, then the memory element has to be
first transferred to an appropriately sized temporary register.</STRIKE>

Section 15.2.1 Syntax
of the value change dump file
 Value changes for real variables are specified
by real numbers. Value changes for all other variables are specified
in binary format by 0,1,x, or z values. Strength information and arrays
(including memories which are one dimensional
arrays) are not dumped.
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Stefen Boyd
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