B07 Proposed wording

From: Anders Nordstrom (andersn@nortel.ca)
Date: Sun May 31 1998 - 12:14:52 PDT

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BAD MSG:
Dear BTF members,
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Status: RO

This enhancement request was passed by the BTF in March last year.
Please review the proposed LRM changes before the June 4 conference call.

Regards,

Anders

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<H2> B07- Comma separated sensitivity list </H2>

<TABLE BORDER COLS=2 WIDTH="75%" >
<TR><TD>
Section: </TD><TD> 9.7.4 page 116
</TD></TR><TR><TD>
Date Submitted: </TD><TD> 970218
</TD></TR><TR><TD>
Requestor: </TD><TD> cliffc@europa.com (Cliff Cummings)
</TD></TR><TR><TD>
Status: </TD><TD> Passed by BTF 3/31/97
</TD></TR><TR><TD>
Analyzed by: </TD><TD> Anders Nordstrom
</TD></TR><TR><TD>
Synthesizable: </TD><TD> Yes
</TD></TR>
</TABLE>

<H3> Details </H3>

Add comma separated sensitivity lists to Verilog
to simplify Verilog modeling capability

Abstract: Standard Verilog sensitivity lists currently require "or"
separators which makes Verilog more verbose than VHDL. Example:
<PRE>
  always @(a or b or c or d or e)
</PRE>
Permit comma-separated and "or"-separated sensitivity lists. Examples:
<PRE>
  always @(a, b, c, d, e) // appropriate usage
  always @(posedge clk, negedge rstn) // appropriate usage

always @(a or b, c, d or e) // clumsy, permitted but not encouraged?
</PRE>
Should the last example be permitted??
<BR>
This enhancement request will not break any existing Verilog models.
<BR>
===== Notes from BTF meeting held at IVC on 3/31/97=====
<BR>
Comma-separated sensitivity lists shall be synonymous to or-separated
sensitivity lists.

<H3> Proposal </H3>

<p>Section 9.7.4 page 116: Change the sentence "The keyword <B>or</B> is
used as an event logical or operator" to:

"The keyword <B>or</B>, a comma character (,) or a combination of
both is used as an event logical or operator."

Add the following sentence at the end of the first paragraph in
section 9.7.4: <BR>
Comma-separated sensitivity lists shall be synonymous to or-separated
sensitivity lists.

Add the following examples at the end of section 9.7.4 on page 116:
<PRE>
  always @(a, b, c, d, e)
  always @(posedge clk, negedge rstn)
  always @(a or b, c, d or e)
</PRE>
<BR>
Add the following line to Syntax 9-1 on page 100 and Syntax 9-8 on page 114
after "| event_expression <B>or</B> event_expression" and to the syntax for
event_expression in Annex A.6 on page 599:
<PRE>
        | event_expression <B>,</B> event_expression
</PRE>

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