Re: generate.html

From: Adam Krolnik (adamk@cyrix.com)
Date: Mon Jul 20 1998 - 02:41:15 PDT


Good morning,

WARNING: There is a request towards the end for the ability to generate within
a procedural block/task/funcion.

<p>Some comments on the generate wording.

The paragraph that starts with "Generated instantiations allow one
or more modules, user defined primitives..." has a long sentence that
tries to specify too many things. Consider it tries to do this:

1. How many things can be instantiated/created => 1 or more.
2. What can be instantiated/created? => Modules, primitives, UDP's, etc.
3. Is there control over alternatives? => Yes, conditional generation.

I would rather see a more sentences that are understandable. Also, not all things
that can be specified in a generate block can be instantiated (declarations,
defparms, assign statements, initial/always blocks).

How about:

"Generate statements allow instantion of modules, UDP's, and gate primitives."

Speak about conditional generation when you introduce the generate-conditional.
Don't speak about the numbers of things - implicitly, there is no restriction.
Add the assign statement and initial/always block wording to the second
paragraph (where it belongs.)

"realtime and event." would be,

"realtime, event. Continuous assignment as well as initial and always blocks
are also allowed."

<p>Remove this sentence in the paragraph about tasks and functions. It is misplaced,
and misleading!

"; however, automatic (recursively generated) tasks and functions shall not be
hierarchically referenced."

I would word this sentence (to be placed in the section on automatic task definition)
as:

"State in tasks reentered, and state in functions recursively called, is
inaccessible by hierarchical reference. Only the state of the first call instance
is available."

<p>Example with generate-case, generating a task...
I am not liking this now that I try to write one. You have to generate an entire
task instead of just the body!

NOTE: I would like to ask for an ammended grammar allowing generate statements
in addition to 'statement' in tasks/functions and initial/always blocks.
The ability to generate additional statements without having to
duplicate all the beginning information would reduce errors!

<p>// Here is an example with a generate-case example. I was going to add the task
// declaration into the example, but I have found a hugh problem.
module dimm;
  parameter MEM_SIZE = 8, // in mbytes
            MEM_WIDTH = 16;
    input [11:0] adr;
    input [1:0] ba;
    input rasx, casx, csx, wex;
    input [7:0] dqm;
    input cke;
    input [7:0] ds;
    inout [63:0] data;
    input [3:0] clk;

    wire rasb, casb, csb, web;
    wire [7:0] bex;
  
    genvar i;

    generate
       case ({MEM_SIZE, MEM_WIDTH})
         {4'd8, 5'd16}: // 8Meg 16 bits wide.
           begin
           for (i=0;i<4;i = i + 1)
             begin
             sms_16b216t0 p
               (.clk(clk), .csb(csx), .cke(cke), .ba(ba[0]), .addr(adr[10:0]),
                .rasb(rasx), .casb(casx), .web(wex), .udqm(dqm[2*i+1]), .ldqm(dqm[2*i]),
                .dqi(data[15+16*i:16*i]), .dev_id(dev_id3[4:0])
               );
             end
           task read_mem;
             input [31:0] address;
             output [63:0] data;
             begin
             p[3].read_mem(address, data[63:48]);
             p[2].read_mem(address, data[47:32]);
             p[1].read_mem(address, data[31:16]);
             p[0].read_mem(address, data[15:0]);
             end
           endtask
           end
         {4'd16, 5'd16}: // 16Meg 16 bits wide.
           begin
           for (i=0;i<4;i = i + 1)
             begin
             sms_16b208t0 p
               (.clk(clk), .csb(csx), .cke(cke), .ba(ba[0]), .addr(adr[10:0]),
                .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[i]), .dqi(data[8+8*i:8*i]),
                .dev_id(dev_id7[4:0])
               );
             end
           // Man, I have to rewrite the declaration. Yes, it's small, but more
           // code as I include more ways to generate a dimm. Plus, I could have
           // generated these lines if I had access to the generate-for loop!
           task read_mem;
             input [31:0] address;
             output [63:0] data;
             begin
             p[7].read_mem(address, data[63:56]);
             p[6].read_mem(address, data[55:48]);
             p[5].read_mem(address, data[47:40]);
             p[4].read_mem(address, data[39:32]);
             p[3].read_mem(address, data[31:24]);
             p[2].read_mem(address, data[23:16]);
             p[1].read_mem(address, data[15:8]);
             p[0].read_mem(address, data[7:0]);
             end
           endtask
        ...
       endcase
    endgenerate

endmodule



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