From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Tue Jul 21 1998 - 04:40:17 PDT
BAD MSG:
Gate and switch level delays are inertial, I believe,
ut I did not see any statement in Section 7 that it is or is not.
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In Section 6, there is such a statement regarding continuous
assignments, at the end of 6.1.3, but that statement relates
to continuous assignments only.
After further thought, there are additional ambiguities.
What about procedural assignments, for example?
I think this subject requires a more general treatment,
maybe in Section 5 (Scheduling).
Also, it is not clear to me what happens if the
"glitch" width is the same as the delay, so that the
input changes again at the same timepoint in which the
output is supposed to change.
The current language talks about the RHS changing before a
previous change has had time to propagate to the LHS.
It sounds like in certain cases where the glitch and delay widths are equal,
the RHS might change first,
in others the LHS might change first, and in yet others either
the RHS or LHS might change first depending on how the simulator
implements the scheduling.
Is that what we want ?
Sincerely,
Shalom Bresticker
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Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
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