B01 erratta

From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Jul 28 1998 - 21:34:00 PDT

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Hi Kurt,

Wasn't going to do this, but I noticed you didn't correctly specify the
instance names for the example with the task generation.

Changes include:

1. Minor grammar problems (bad tense, additional if/of/).
2. Redundant use of word 'Verilog' in few places.
3. rename 'module instance statement #' to 'named or ordered parameter value assignment'

Adam

*** B01_generate-396-24.html Wed Jul 29 09:59:19 1998
--- B01_generate-addendum.html Wed Jul 29 10:25:53 1998
***************
*** 21,27 ****
 declared in a module can be overridden. It describes
 how generated instantiations can be used to do
 
! conditionally or multiple instantiations in a design.

on page 11 add:
--- 21,27 ----
 declared in a module can be overridden. It describes
 how generated instantiations can be used to do
 
! conditional or multiple instantiations in a design.

on page 11 add:
***************
*** 41,50 ****

Verilog HDL localparam - local parameter(s)
 are identical to parameters except that they can not directly be modified
! with the defparam statement or by the module instance statement
! #. Local parameters can be assigned to a constant expression
 containing a parameter which can be modified with the defparam statement
! or by the module instance statement #. See Section 12.1.3
 for details.

The syntax for local parameter declarations is
--- 41,49 ----

Verilog HDL localparam - local parameter(s)
 are identical to parameters except that they can not directly be modified
! with the defparam statement or by the ordered or named parameter value assignment. Local parameters can be assigned to a constant expression
 containing a parameter which can be modified with the defparam statement
! or by the ordered or named parameter value assignment. See Section 12.1.3
 for details.

The syntax for local parameter declarations is
***************
*** 81,87 ****
 because that is when the parameters associated with a module become defined,
 hence, allowing the definition of the generated statements and declarations.
 Genvars are only defined during the evaluation of the generate instantiations
! (see section 12.1.3), and do not exist during simulation of a Verilog design.
 
 Generate statements facilitate the creation of
 parameterized models. When used with constant functions (see section 10.3.5),
--- 80,86 ----
 because that is when the parameters associated with a module become defined,
 hence, allowing the definition of the generated statements and declarations.
 Genvars are only defined during the evaluation of the generate instantiations
! (see section 12.1.3), and do not exist during simulation of a design.
 
 Generate statements facilitate the creation of
 parameterized models. When used with constant functions (see section 10.3.5),
***************
*** 108,115 ****
 identifier names and can be referenced hierarchically as described in section
 12.4 .
 
! Parameter redefinition using module instance
! statement # or defparam statements can also be declared within
 the generate scope.
 
 Tasks and functions declarations shall also be
--- 107,113 ----
 identifier names and can be referenced hierarchically as described in section
 12.4 .
 
! Parameter redefinition using by the ordered or named parameter value assignment or defparam statements can also be declared within
 the generate scope.
 
 Tasks and functions declarations shall also be
***************
*** 262,272 ****

Section 12.1.3.2 Generate-loop
 
! A generate-loop permits one or more of
! variable declarations, defined modules, user defined primitives, Verilog
 gate primitives, continuous assignments, initial blocks and always blocks
! to be instantiated multiple times using an indexed for-loop. The index
! loop-variable used in a generate for-loop shall be declared as a genvar.

Example 1 - A parameterized gray-code to binary-code
converter module using a loop to generate continuous assignments
--- 260,270 ----

Section 12.1.3.2 Generate-loop
 
! A generate-loop permits one or more
! variable declarations, modules, user defined primitives,
 gate primitives, continuous assignments, initial blocks and always blocks
! to be instantiated multiple times using a for-loop. The index
! loop variable used in a generate for-loop shall be declared as a genvar.

Example 1 - A parameterized gray-code to binary-code
 converter module using a loop to generate continuous assignments
***************
*** 611,616 ****
--- 609,616 ----
 endtask</TT>
 <TT>
 end</TT>
+ <TT> // The generated instance names are
+ p[3], p[2], p[1], p[0] and the task read_mem</TT>
 <TT>
 {'d16, 'd8}: // 16Meg 8 bits wide.</TT>
 <TT>
***************
*** 663,670 ****
 .....</TT>
 <TT> endcase</TT>
 <TT> endgenerate</TT>
! <TT> // The generated instance name is
! p, and the task read_mem</TT>
 
 <TT>endmodule</TT>
 
--- 663,670 ----
 .....</TT>
 <TT> endcase</TT>
 <TT> endgenerate</TT>
! <TT> // The generated instance names are
! p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0], and the task read_mem</TT>
 
 <TT>endmodule</TT>
 
***************
*** 710,716 ****
 <HR WIDTH="100%">
 hierarchical_identifier ::=
 
! hierarchical_branch [ { .hierarchical_branch } ]

hierarchical_branch ::=
 
--- 710,716 ----
 <HR WIDTH="100%">
 hierarchical_identifier ::=
 
! hierarchical_branch [ { . hierarchical_branch } ]

hierarchical_branch ::=

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