From: Adam Krolnik (adamk@cyrix.com)
Date: Wed Aug 12 1998 - 23:23:19 PDT
Hello Kurt,
I have a couple of questions regarding the limitations of the
generate statements.
Why was there a restriction to not generate ports? Consider this
example I wrote. It is a variable width/depth Q. Typically, designers
need access to the internal Q state for such things as comparisons
usage of information, etc. Yet, one can't generate outputs
based on a parameter.
Also, how would you perform error checking on parameters of a module
to ensure correct values. I.e. consider this example. It is an error
to try to instantiate a module with a depth less than 1.
Also, still disappointed at lack of generate inside begin..end pair.
Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
<p>// Generic Q module. Has data input and output ports, Q data output ports.
// has controls, store (incoming data), clear (Q), clk
// and status signals, full, empty.
// Width and depth are specified as parameters via respective name.
module flowQ;
parameter width = 32,
depth = 8;
input[width-1:0] dataIn;
output[width-1:0] dataOut;
input store, clear, clk;
output full, empty;
genvar ith;
generate
for(ith=0; ith < depth; ith = ith + 1)
output [width-1:0] q[ith];
endgenerate
wire [depth-1:0] load, v_in, valid;
wire shift;
generate
// Min depth is 1!
dflop #(.width(width)) d[0] (.d(dataIn), .q(q[0]), .clk(clk),
.clr(clear), .ld(shift|load[0]));
dflop #(.width(depth)) valid_entry (.d(v_in), .q(valid),
for(ith = 1; i< depth; ith = ith + 1)
begin
wire [width-1:0] q[ith],
d2flop #(.width(width)) d[ith] (.d1(q0), .d0(dataIn),
.q(q[ith]), .clr(clear),
.clk(clk), .ld({shift, load[ith]}));
end
endgenerate
ctl_logic #(.depth(depth)) ctl(store, full, empty, valid, v_in,=
shift, load);
// Either flow-thru (for the empty case) or select the last element.
assign dataOut = empty ? dataIn : q[width-1];
endmodule
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