From: Anders Nordstrom (Anders.Nordstrom.andersn@nt.com)
Date: Tue Aug 25 1998 - 10:20:54 PDT
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From: "John H. E. Fiskio-Lasseter" <johnfl@cs.uoregon.edu>
Newsgroups: comp.lang.verilog
Subject: Is expression evaluation well defined?
Date: Sat, 22 Aug 1998 15:34:33 -0700
Organization: University of Oregon, Eugene
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One of the potential hazards of concurrent programming languages in
general is that a variable that occurs multiple times within an
expression E may change value in the middle of an evaluation of E. In
such cases *the* value of E is not necessarily well defined from any
given initial state.
I believe that the Verilog semantics are open to this hazard, vis-a-vis
the behavioral constructs, but I cannot find anything in the IEEE
Standard that indicates either way.
For example:
initial begin x = 1; if ((!x) || x) some_statement; end
initial x = 0;
Will some_statement execute? In almost every case, yes, but we
cannot guarantee it. Suppose we first perform the assignment of
x to 1, followed immediately by an evaluation of the (!x) portion of the
if-expression (which will evaluate to 0). Now perform the assignment of
x to 0, followed by the evaluation of the rest of the boolean or
expression. Now, x has the value 0 in memory, so the whole
expression evaluates to (0 || 0) = 0, and some_statement will not
execute.
Can anyone provide a reference to a passage in the IEEE Standard that
contradicts this analysis?
-- John
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Wit, an' it be thy will, put me into good fooling. Those wits
who think they have thee do very oft prove fools, while I, who
am sure I lack thee, may yet pass for a wise man. For what
says Quinapalus -- "Better a witty fool than a foolish wit".
_Twelfth Night_
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