Re: [Fwd: Is expression evaluation well defined?]

From: John H. E. Fiskio-Lasseter (johnfl@cs.uoregon.edu)
Date: Wed Aug 26 1998 - 09:44:41 PDT


On Wed, 26 Aug 1998, Shalom Bresticker wrote:
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> I tend to agree with Mr. Fiskio-Lasseter.
> In fact, I warned about similar problems 3 years (June 1995) during the
> vote on 1364-1995.
> I think the arguments I made were valid then and are still valid.
> I don't think the problems have been satisfactorily dealt with since then.
>
> The key is section 5.4.2 "Nondeterminism", which states that:
> "At any time when evaluating a behavioral statement, the simulator may
> suspend execution and place the partially completed event as a pending
> active event on the event queue.
>
> The effect of this is to allow the interleaving of process execution.
> Note that the order of interleaved execution is nondeterministic andnot
> under control of the user."
>
> In fact, it seems that Mr. Fiskio-Lasseter has shown that the problem
> is more severe than even I thought!

Mr. Bresticker,

Thanks for forwarding your analysis of this. I haven't had time to read
it yet (I just turned in my MS thesis to the graduate school this morning,
and I'm about to take a few well-deserved days off). I've forwarded it
to my advisor, and will try to kick back with it in a day or two.
 
Actually the most interesting point comes from the fact that if full
interleaving like this is allowed, then I don't think that the requirement
that all eligible guards must fire when their event occurs (section 5.2)
can be guaranteed. If this is true then the semantics as defined
informally in 1364 contain a contradiction.

I'm not confident enough about this to go on record about it, but my
advisor and I are looking at it in the next couple of weeks as we try to
get together a paper for the IVC. In my thesis, I only mention it in a
closing paragraph (I only figured it out last week, and didn't feel that I
had time to really do it justice).

Actually, would you be interested in reading the thesis? My work involved
contructing a formal semantics of most of the behavioral subset of
Verilog, based on an axiomatic description. It's not terribly useful from
the point of view of industry, since it produces terrible code, but I
found some interesting minutiae about the semantics in the course of
developing the axioms. I'd be very interested in your feedback and
whether you think our ideas are on track.

On the other hand, if you really don't have the time for it, I'd
understand. Do let me know, and I'll send you a pointer to it.

Peace,
-- John
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Wit, an' it be thy will, put me into good fooling. Those wits
who think they have thee do very oft prove fools, while I, who
am sure I lack thee, may yet pass for a wise man. For what
says Quinapalus -- "Better a witty fool than a foolish wit".
                                               _Twelfth Night_
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