From: Cliff Cummings (cliffc@sunburst)
Date: Fri Oct 30 1998 - 11:56:10 PST
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Hierarchical names must state how the following are defined and referenced:
<BR>1995> Escaped identifiers
<BR>1995> Parallel root modules
<BR>1998> Generated instances
<BR>1995> Arrayed-instance identifiers
<BR>1998> Multidimensional arrays
<BR>1998> Recursive tasks and functions (shall not be hierarchically referenced)
<BR>
<BR><FONT COLOR="#FF0000">{} - proposed changes</FONT>
<BR>
<H2>
12.4 Hierarchical names</H2>
<BR>Every identifier in a Verilog HDL description shall have a unique <I>hierarchical
path name</I>. The hierarchy of modules and the definition of items such
as tasks and named blocks within the modules shall define these names.
The hierarchy of names can be viewed as a tree structure, where each module
instance, task, function or named <TT>begin-end</TT> or <TT>fork-join</TT>
block defines a new hierarchical level, or scope, in a particular branch
of the tree.
<BR>
<BR>At the top of the name hierarchy are the names of <FONT COLOR="#FF0000">{one
or more root}</FONT> modules for which no instances have been created.
<STRIKE><FONT COLOR="#3366FF">It is the root of the hierarchy.</FONT></STRIKE>
<FONT COLOR="#FF0000">{This root or these parallel root modules make up
one or more hierarchies in a "design description" or "description".} </FONT>Inside
any module, each module instance <FONT COLOR="#FF0000">{(including an arrayed
or generated instance)}</FONT> , task definition, function definition,
and named <TT>begin-end </TT>or <TT>fork-join</TT> block shall define a
new branch of the hierarchy. Named blocks within named blocks and within
tasks and functions shall create new branches. <FONT COLOR="#FF0000">{Only
non-recursively referenced automatic tasks and/or functions create visible
branches that can be referenced. Recursively called tasks and functions,
declared using the automatic keyword and recursively called from within
the same task or function, do not create visible branches that can be referenced.
See section </FONT><FONT COLOR="#006600">???</FONT><FONT COLOR="#FF0000">
for a discussion of automatic tasks and functions.}</FONT>
<BR>
<BR>Each node in the hierarchical name tree shall be a separate scope with
respect to identifiers. A particular identifier can be declared at most
once in any scope. See section 12.5 for a discussion of scope rules and
section 3.11 for a discussion of name spaces.
Any named Verilog object <FONT COLOR="#FF0000">{or "hierarchical name
reference"}</FONT> can be referenced uniquely in its full form by concatenating
the names of the modules, <FONT COLOR="#FF0000">{module instance names,}</FONT>
tasks, functions, or blocks that contain it. The period character shall
be used to separate each of the names in the hierarchy <FONT COLOR="#FF0000">{,
except for escaped identifiers embedded in the hierarchical name reference,
which are followed by separators composed of white space and a period-character}</FONT>
. The complete path name to any object shall start at a top-level <FONT COLOR="#FF0000">{(root)}</FONT>
module. This path name can be used from any level in the <STRIKE><FONT COLOR="#3333FF">description</FONT></STRIKE>
<FONT COLOR="#FF0000">{hierarchy or from a parallel hierarchy}</FONT> .
The first node name in a path name can also be the top of a hierarchy that
starts at the level where the path is being used. <FONT COLOR="#FF0000">{The
latter allows and enables downward referencing of items.}</FONT>
<BR><FONT COLOR="#FF0000"> </FONT>
<BR><I>Examples:</I>
<BR>
<BR><I>Example 1</I> - The code in this example defines a hierarchy of
module instances and named blocks. Figure 12-1 illustrates the hierarchy
implicit in this Verilog code. Figure 12-2 is a list of the hierarchical
forms of the names of all the objects defined in the code.
<BR>
<BR>
<BR><B><TT><FONT SIZE=+2>
wave</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2>
|</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> +-----+-----+</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> |
|</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> a
wave1</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> |
|</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> +---+---+
|</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> | |
|</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2>amod bmod
innerwave</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2> | |</FONT></TT></B>
<BR><B><TT><FONT SIZE=+2>keep keep</FONT></TT></B>
<BR>
<BR><B>Figure 12-1 - Hierarchy in a model</B>
<BR>
<TT>wave
wave.a.bmod</TT>
<BR><TT>wave.stim1
wave.a.bmod.in</TT>
<BR><TT>wave.stim2
wave.a.bmod.keep</TT>
<BR><TT>wave.stim1
wave.a.bmod.keep.hold</TT>
<BR><TT>wave.a.stim1
wave.wave1</TT>
<BR><TT>wave.a.stim2
wave.wave1.innerwave</TT>
<BR><TT>wave.a.amod
wave.wave1.innerwave.hold</TT>
<BR><TT>wave.a.amod.in</TT>
<BR><TT>wave.a.amod.keep</TT>
<BR><TT>wave.a.amod.keep.hold</TT>
<BR>
<BR><B>Figure 12-2 - Hierarchical path names in a model</B>
<BR>
Hierarchical name referencing allows free data access to any object
from any level in the {same or parallel} hierarchy. If the unique hierarchical
path name of
<BR>an item is known, its value can be sampled or changed from anywhere
within the description.
<BR>
<BR><I>Example 2</I> - The next example shows how a pair of named blocks
can refer to items declared within each other.
<BR>
<BR><TT> <B>begin</B></TT>
<BR><TT> <B>fork</B>: mod_1</TT>
<BR><TT> <B>reg</B> x;</TT>
<BR><TT> mod_2.x = 1;</TT>
<BR><TT> <B>join</B></TT>
<BR><TT> </TT>
<BR><TT> <B>fork</B>: mod_2</TT>
<BR><TT> <B>reg</B> x;</TT>
<BR><TT> mod_1.x = 0;</TT>
<BR><TT> <B>join</B></TT>
<BR><TT> <B>end</B></TT>
<BR>
<BR>
<H3>
12.4.1 Upwards name referencing</H3>
<BR>A lower-level module can reference items in a module above it in the
hierarchy if the name of the higher-level module is known. The syntax for
an upward referen
<BR>ce is given in Syntax 12-5.
<BR>
<BR><TT>upward_name_reference ::=</TT>
<BR><TT> module_identifier.item_name</TT>
<BR><TT>item_name ::=</TT>
<BR><TT> port_identifier</TT>
<BR><TT> | reg_identifier</TT>
<BR><TT> | net_identifier</TT>
<BR><TT> | parameter_identifier</TT>
<BR><TT> | function_identifier</TT>
<BR><TT> | task_identifier</TT>
<BR><TT> | named_block_identifier</TT>
<BR>
<BR><I>Syntax 12-5 - Syntax for upward name referencing</I>
<BR>
Upwards name references can also be done with names of the form
<BR>
<BR><TT> module_instance_name.item_name</TT>
<BR>
<BR>A name of this form shall be resolved as follows:
<BR> a) Look in the current module for a module instance named
<TT>module_instance_name</TT>. If found, this name reference shall be treated
as a downward reference, and the item name shall be resolved in the corresponding
module.
b) Look in the parent module for a module instance named <TT>module_instance_name</TT>.
If found, the item name shall be resolved from that instance, which is
the sibling of the module containing the reference.
c) Repeat step b), going up the hierarchy.
<BR>
<BR>There shall be no spaces within the hierarchical name reference <FONT COLOR="#FF0000">{,
except for escaped identifiers embedded in the hierarchical name reference,
which are followed by separators composed of white space and a period-character}</FONT>
.
<I>Example:</I>
<BR>
<BR>In this example, there are four modules, <TT>a</TT>, <TT>b</TT>, <TT>c</TT>,
and <TT>d</TT>. Each module contains an integer <TT>i</TT>. The highest-level
modules in this segment of a model hierarchy are <TT>a</TT> and <TT>d</TT>.
There are two copies of module <TT>b</TT> because module <FONT FACE="Arial,Helvetica">a</FONT>
and <TT>d</TT> instantiate <TT>b</TT>. There are four copies of <TT>c.i</TT>
because each of the two copies of <TT>b</TT> instantiates <TT>c</TT> twice.
<BR>
<BR><FONT COLOR="#FF0000">{The name of a module or module instance is sufficient
to identify the module and its location in the hierarchy. A lower-level
module can reference items in a module above it in the hierarchy. For variables
they can be referenced if the name of the higher-level module or its instance
name is known. For tasks, functions and named blocks, Verilog will look
in the enclosing module for the name, until it is found or until the root
of the hierarchy is reached. It will only search in higher enclosing modules
for the name, not instances. The syntax for a hierarchical reference is
as follows:</FONT>
<BR><FONT COLOR="#FF0000"> </FONT>
<BR><FONT COLOR="#FF0000"> <name_of_module_or_instance>.<name_of_item></FONT>
<BR><FONT COLOR="#FF0000"> </FONT>
<BR><FONT COLOR="#FF0000">There can be no spaces within the reference,
except for escaped identifiers embedded in the hierarchical name reference,.
Example 12-11 demonstrates upward referencing. In this example, there are
four modules, mod_a, mod_b, mod_c and mod_d. Each module contains an integer
x. The highest level modules in this segment of a model hierarchy are mod_a
and mod_d. There are two copies of module mod_b.x because both mod_a and
mod_d both instantiate mod_b.X. There are four copies of mod_c.x because
each of the two copies of mod_b.x instantiates mod_c.x twice. }</FONT>
<BR>
<BR>
<BR>12.5 Scope rules
<BR>
<BR>The following four elements define a new scope in Verilog:
<BR>
<BR> - Modules
<BR> - Tasks
<BR> - Function
<BR> - Named blocks
<BR>
<BR>An identifier shall be used to declare only one item within a scope.
This rule means it is illegal to declare two or more variables that have
the same name, or to name a task the same as a variable within the same
module, or to give a gate instance the same name as the name of the net
connected to its output.
<BR>
<BR>If an identifier is referenced directly (without a hierarchical path)
within a task, function or named-block, it shall be declared either locally
within the task, function or named block, or within a module, task or named
block that is higher in the same branch of the name tree that contains
the task, function, or named block. If it is declared locally, then the
local item shall be used; if not, the search shall continue upward until
an item by that name is found or until a module boundary is encountered.
<FONT COLOR="#FF0000">{If the item is a variable, it will stop at a module
boundary; if the item is a task, function, or named block it continues
to search higher-level modules until found.}</FONT> The search <FONT COLOR="#FF0000">{for
variables}</FONT> shall cross named block, task and function boundaries
but not module boundaries. This fact means that tasks and functions can
use and modify the variables within the containing module by name, without
going through their ports.
<BR>
<BR><FONT COLOR="#FF0000">{If an identifier is referenced with a hierarchical
name, the path can start with an module name, instance name, task, function,
or named block. The names will be searched first at the current level,
then in higher-level modules until found. Since both module names and instance
names can be used, precedence is given to instance names if there is a
module named the same as an instance name.}</FONT>
<BR>
<BR>Because of the upward searching, path names that are not strictly on
a downward path can be used.
<BR>
<BR><I>Example:</I>
<BR>
<BR><I>Example 1</I> - In Figure 12-3, each rectangle represents a local
scope. The scope a vailable to upward searching extends outward to all
containing rectangles - with the boundary of the module A as the outer
limit. Thus block G can directly reference identifiers in F, E, and A;
it cannot directly reference identifiers in H, B, C and D.
<BR><I> </I>
<BR><B><I><Figure 12-3></I></B>
<BR>
<BR><B>Figure 12-3 - Scopes available to upward name referencing</B>
<BR>
<BR><I>Example 2</I> - The following example shows an incompletely defined
downward reference that can be accessed.
<BR>
<BR><TT> <B>task</B> t;</TT>
<BR><TT> <B>reg</B> r, s;</TT>
<BR><TT> <B>begin</B>: b</TT>
<BR><TT> // redundant assignments
to reg r</TT>
<BR><TT> t.b.r = 0; //
poorly defined but found by upward search</TT>
<BR><TT> t.<STRIKE><FONT COLOR="#3366FF">s</FONT></STRIKE><FONT COLOR="#FF0000">{r}</FONT>
= 0; // fully defined downward reference</TT>
<BR><TT> <B>end</B></TT>
<BR><TT> <B>endtask</B> </TT>
<BR>
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