From: Michael McNamara (mac@surefirev.com)
Date: Wed Nov 18 1998 - 17:55:43 PST
How about this:
/* Proposal for the new partselect operators [ +: ] and [ -: ]:
SIGNAL [ ANCHOR +: WIDTH]
SIGNAL [ ANCHOR -: WIDTH]
ANCHOR may be any verilog expression. WIDTH may be any verilog
constant expression. SIGNAL is any verilog net or register.
The SIGNAL is deemed big endian if the declaration of SIGNAL is
such that the value of the msb is larger than the lsb. The SIGNAL
is deemed little endian if the declaration of SIGNAL is such that
the value of the msb is smaller than the lsb. For example:
reg [7:0] a; // a big endian signal
reg [4:40] b; // a little endian signal
The operator +: specifes:
* ANCHOR is evaluated to yeild a value.
* WIDTH is enaluated to yeild a value.
* If SIGNAL is big endian, than WIDTH bits starting at position
ANCHOR+WIDTH-1 through position ANCHOR are selected.
* If SIGNAL is little endian, than WIDTH bits starting at position
ANCHOR through position ANCHOR+WIDTH-1 are selected.
The operator -: specifes:
* ANCHOR is evaluated to yeild a value.
* WIDTH is enaluated to yeild a value.
* If SIGNAL is big endian, than WIDTH bits starting at position
ANCHOR through bit position ANCHOR-(WIDTH-1) are selected.
* If SIGNAL is little endian, than WIDTH bits starting at position
ANCHOR-(WIDTH-1) through position ANCHOR are selected.
An example: In the following code, the first two always blocks
specify the same behaviour, both which, if sel had the value 2, are
equivalent to the third always block.
*/
module foo(clk,sel);
input clk;
input [3:0] sel;
reg [7:0] blue;
reg [0:7] green;
// currently proposed syntax
always @(clk) begin
if ( blue[sel+3:sel] === green[sel:sel+3] )
$display("Match A!");
if ( blue[sel:sel-1] === green[sel-1:sel] )
$display("Match B!");
if ( blue[sel+2:sel+2-1] === green[sel+2-1:sel+2] )
$display("Match C!");
end // always @ (clk)
// an alternative syntax
always @(clk) begin
if ( blue[sel+:3] === green[sel+:3] )
$display("Match A!");
if ( blue[sel-:1] === green[sel-:1] )
$display("Match B!");
if ( blue[sel+2 -: 1] === green[sel+2 -: 1] )
$display("Match C!");
end // always @ (clk)
// the equivalent form if sel === 2
always @(clk) begin
if ( blue[5:2] === green[2:5] )
$display("Match A!");
if ( blue[2:1] === green[1:2] )
$display("Match B!");
if ( blue[4:3] === green[3:4] )
$display("Match C!");
end // always @ (clk)
endmodule // foo
<p>/* Things to note:
Recognize that the syntax that has been proposed requires the coder
to know at point of use the endianess of the object of the part
select. The newly proposed syntax does not require such knowledge.
Another disadvantage of the current proposal is that the user has
to type the varient part twice. This is irritating, if the varient
is a variable, painfull if it is an expression, and ambiguous if it
is a function call (which could yeild different answers if called
twice).
An advantage of the current proposal is that there is no new
syntax; folks will reasonably understand what the code means, and
quite possibly have typed similar code in the past and gotten:
Error! Non-constant part-select index [Verilog-NCPSI]
"ind.v", 9: blue[sel:sel + 3]
The second proposal uses new syntax for this new behaviour, and is
designed to be unambiguous as to what goes where. The first
argument can be any verilog expression, and is evaluated to
determine the anchor of the part select. The second argument must
be a compile time constant, and specifies the width of the
partselect. It is not possible in the new syntax to specify a Wrong
Way part select.
The +: operator ("select up") says we should select bits that range
from the anchor to the width-1 bits more signifigant than the
anchor.
The -: operator ("select down") says we should select bits that
range from the position of the anchor to the position width-1 bits
less signifigant than the anchor.
*/
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