From: Michael McNamara (mac@surefirev.com)
Date: Thu Nov 19 1998 - 09:25:07 PST
Stefen Boyd writes:
> At 07:19 PM 11/18/98 -0800, Michael McNamara wrote:
> >So, you like the behavior of '+:', but would rather call it '::', and
> >see no reason to give the user the ability to do '-:'
> >
> Sorta... '+:' goes from lowbit to high bit. '::' goes from left to
> right.
> wire [7:0] green;
> wire [0:7] blue;
>
> green[3+:2] == green[4:3];
> blue[3+:2] == blue[3:4];
>
> but with '::'
> green[3::2] == green[3:2];
> blue[3::2] == blue[3:4];
>
>
>
> >I think we all agree that the *&*!@ tool should figure out endiness
> >and deal with it.
>
> I just want to go for something that is the most
> intuitive to the user. The idea that [8+:2] might
> have the 8 in the second part of the select [x:8]
> feels backwards.
Conversly, I feel that for orthogonality, in a design, it
might be reasonable to want to specify, "operate on the two bits of
data starting from 8 counting up", and "operate on the two bits of
data starting from 8 counting down".
>
> My only hesitation with '::' is that Verilog-2010
> might want to use '::' to access static members of
> a class...
Ahh, I had to get back up off the floor after reading that
sentence! :-)
-mac
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