Attributes in Verilog

From: Tom Fitzpatrick (tfitz@cadence.com)
Date: Wed Jan 06 1999 - 07:00:57 PST

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Attributes are a very useful feature that we are currently using in
Verilog-XL, and NC-Verilog. We mostly use them to identify things like VHDL
modules for mixed-language simulation, and identifying modules that may be
cycle simulated. These could also be extended to include library and view
information with the new config proposal which will be coming out soon.
I've included the proposed BNF below.

module top(b,c);
  output b;
  reg clk,a;
  wire b,c;

  // instantiate a vhdl module here:
  vhdlmod vhdlmod(clk,a,b);

  // instantiate a cycle-sim module here:
  cyclemod (* const integer cycle = 1; *) cyclemod(clk,a,c);
endmodule

module vhdlmod(clk,a,b) (* const integer foreign = "VHDL WORKLIB.E:a"; *);
  input clk,a;
  output b;
...
endmodule

We currently only allow for attribute types to be integer, time or real.
Since there is no real string type in Verilog, this leads to the 'integer
foreign = "string"' syntax above, which some people may think looks kind of
strange. We could extend the type list to include "string".

Your questions and comments are welcome.
Thanks,
-Tom

<p>Here's the BNF:

This is what an attribute is:
    <instance_attr> ::= (* <attr_list> *)

    <attr_list>::
        ::= <attr><,attr>*

    <attr>
        ::= [CONST] <type><attr_spec_list>;

    <attr_spec_list>
        ::= <attr_spec><,attr_spec>*

    <attr_spec>
        ::= <attr_name> = <value>
        ||= <attr_name>

    <value>
        ::= <constant>
        ||= <constant_expression>

    <type>
        ::=integer
        ||=time
        ||=real

This is how an attribute is used:
variable instances:

        <type><range>?<instance_attr><instances>+
        <type>
            ::= REG
            ||= TIME
            ||= INTEGER
            ||= INPUT
            ||= OUTPUT
            ||= INOUT
        
        REAL <instance_attr>?<instances>+
        REALTIME <instance_attr>?<instances>+
        EVENT <instance_attr>?<events>+
        
        <net_type><strength>?<expandrange>?<delay>?<instance_attr>?<net_expression>;
        <net_expression>
            ::= <net_name>
            ||= <net_name> = <expression>

gate and switch instances:

        <gate_type> [<drive_strength>] [<delay>] [<instance_attr>]
                        <gate_instance>+;

module and udp declarations and instantiations:

        MODULE <module_name> [<port_list>] [<instance_attr>];
                [<module_item>]

        ENDMODULE

        PRIMITIVE <prim_name> ((port_list) [<instance_attr>];
                <prim_declaration>+
                [<prim_initialization>]
                <table_definition>
        ENDPRIMITIVE

Module or udp ports:
        
        <port_type> [<range>] [<instance_attr>] <list_of_variables>;
        <port_type> ::= INPUT
                ||= OUTPUT
                ||= INOUT

Function and Task declarations and invocations:

        FUNCTION [<range>] <function_name> [<instance_attr>];
                <tf_declarations>+
                [<statement>]
        ENDFUNCTION

        TASK <task_name> [<instance_attr>] ;
                <tf_declarations>+
                [<statement>]
        ENDTASK

built-in operators:

        <unary_op> [<instance_attr>] <expression>

        <expression> <binary_op> [<instance_attr>] <expression>

        ? [<instance_attr>] <expression> : <expression>

---------------
Tom Fitzpatrick

Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438

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