From: Tom Fitzpatrick (tfitz@cadence.com)
Date: Wed Jan 06 1999 - 08:38:26 PST
BAD MSG:
Hi Adam,
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Currently, we use attributes mostly at elaboration time to tell us things
like:
1) Is the module intended to represent a VHDL entity?
module foo(a,b) (* const integer foreign = "VHDL WORKLIB.E:A"; *);
2) Is the module to behave according to cycle-based semantics?
module foo(a,b) (* const integer cycle = 1; *);
or
foo (* const integer cycle = 0; *) event(a,b); // This instance is event
foo (* const integer cycle = 1; *) foo(a,b); // Thisinstance is cycle
for this option, we also include the ability to specify specific build
options to use when compiling the model:
foo (* const integer cycle = 1;
const integer build_options = "-verbosity 3 -keep_all"; *) foo(a,b);
3) Is this input intended to trigger?
input (* const integer trigger = 1; *) clk;
We have batted around the possibility of referring to attributes within the
verilog, something like
if (foo->cycle == 1) $display("Hi, I'm a cycle model");
This could potentially conflict with the future proposed syntax of
referring to records, so we may want to choose a different syntax if the
ability to read attributes within the verilog is deemed necessary. Right
now, I'm not so sure it's required, but I don't think we want to preclude it.
If this were extended to configs, which would be really useful, you could
use them to specify specific bindings for module instantiations:
module mod1();
wire a,b;
foo (* const integer view = "gates_with_timing"; *) foo(a,b);
endmodule
this would force mod1.foo to use the gates_with_timing view while other
instances of foo would take their view from the config.
I see no reason why this couldn't be accessed by a preprocessor.
Thanks,
-Tom
PS. Happy New Year to you, too!
At 09:43 AM 1/6/99 -0600, Adam Krolnik wrote:
>
>Hello Tom, Happy new year.
>
>One thing that isn't very clear is how you use these attributes.
>
>They seem like variables (something that computation can be done on
>and values stored in) but you have the concept of immutable (CONST.)
>They can be an integer, time or real, but (as you point out) no string
>values.
>
>What do you use these for? E.g.
> Can you query them in the Verilog code?
> Are they useful with configuration?
> Does the preprocessor have access to them?
>
>Can you provide a few examples of things with attributs and how they
>are used?
>
>
> Adam Krolnik
> Verification Engineer
> Cyrix - NSC.
> Richardson TX. 75085
>
>
>
>
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438
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