From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Jan 07 1999 - 21:26:07 PST
At 02:59 AM 12/22/98 -0800, you wrote:
<p>BAD MSG:
>Cliff,
>The PTF needs a couple of clarifications on the new automatic functions:
>
>1. What types of functions are intended to be re-entrant: Only automatic
>functions, regular functions with automatic variables, both, or none?
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Charles -
You probably already know much of this but for all those eavesdropping on
this e-mail, let me be somewhat thorough. I hope that other BTF members
would add comments or correct my mistakes in this discussion.
A re-entrant function is a function that is called from two locations (not
recursively), supposedly at the same time.
All functions are re-entrant. Non-blocking assignments and timing controls
are not permitted in a function so if a function is called from two
different places in the Verilog code, the first call will execute and
return a value before the second call is executed.
Re-entrance complexities apply mostly to tasks. Automatic tasks with timing
controls and/or non-blocking assignments can be called from two different
locations, execute simultaneously and use completely different variables.
Verilog-1995 tasks are not re-entrant since they use the same static
variables.
A recursive function is a function that calls itself.
Verilog-1995 functions only have static variables. Verilog-1995 functions
with Verilog-1999 automatic variables might have a mixture of both static
and automatic variables. A Verilog-1999 automatic function only has
automatic variables
>2. Can an old style function contain automatic variables? The description
>on the web seems to say yes, but then is the implied variable for the
>function name still static? How does this behave for re-entrant
>(recursive) function calls?
Old-style functions can declare both normal variables (old style static
variables), automatic variables and the function name would still be static.
There would be no difference between Verilog-1995 and Verilog-1999
functions for re-entrant function calls.
Verilog-1995 recursive function calls would continue to modify the same
static variables while stacking the automatic variables with each recursive
call.
>3. Can static variables be declared in an automatic function? How does
>this behave for re-entrant (recursive) function calls?
All variables in an automatic function are automatic. If automatic
variables are declared inside of an automatic function, the automatic
variable declarations are redundant (since all variables of an automatic
function are automatic). The only reasons I can think of to declare
automatic variables in an automatic function is for debugging or
conditionally compiled coding purposes (Perhaps an `ifdef AUTO would
declare an automatic function where all of the variables were automatic,
while the `else would declare a static function where some of the variables
had been declared to be automatic).
>Stu
I believe the BTF never intended that recursively spawned automatic
functions be hierarchically referenced (what would be the name of the 3rd
recursively called function?) or accessed through the PLI.
Let me know if you have additional questions.
Regards - Cliff
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