BTF B05 - Configuration examples

From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Mon Jan 11 1999 - 10:57:15 PST

BAD MSG:
Hi Gang,
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Status: RO

I'm getting there. These are Cliff's examples using the new
syntax. I've tried to use the exact same directory structure that
Cliff had. Please let me know if you have any questions or comments.

Thanks,
-Tom

--------------------------------------------------------------------------

Cliff's Examples

Invoking from the /root/projects/proj1/tb

All of the multi-adder examples below are intended to give the same
result:

testbench: tb
top instance: tb.top
adder instances from gates directory: tb.top.i2
adder instances from vlog directory: tb.top.i1, tb.top.i3, tb.top.i4

//-----------------------------------------------
// This file: /root/projects/proj1/tb/tb.v
// testbench module
//-----------------------------------------------
module tb;
  ...
  top g1 (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj1/vlog/top.v
// design top-level module
//-----------------------------------------------
module top (...);
  ...
  adder i1 (...);
  adder i2 (...);
  adder i3 (...);
  adder i4 (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj1/vlog/adder.v
// same module name and port list as
// the ../gates/adder.vg module
//-----------------------------------------------
module adder (...);
  ... // RTL adder code
endmodule

//-----------------------------------------------
// This file: /root/projects/proj1/gates/adder.vg
// same module name and port list as
// the ../vlog/adder.v module
//-----------------------------------------------
module adder (...);
  ... // Gate-level adder code
endmodule

//---------------------------------------------------
// File: /root/projects/proj1/tb/lib.map
//---------------------------------------------------
`view gates file ".../*.vg;
`view rtl file ".../*.v;

`library lib1
  file "/root/projects/proj1/gates/adder.vg", // gates view
  file "../vlog/*.v"; // rtl view

//
// default library statement:
// library work;
// file "tb.v;
// endlibrary
//---------------------------------------------------
// end of lib.map
//---------------------------------------------------

//---------------------------------------------------
// This file: /root/projects/proj1/tb/adders1a.cfg
//---------------------------------------------------
config adders1a;
  design work.tb:rtl;
  default liblist lib1;
  path tb.top.i2 viewlist gates;
endconfig

Invocation: verilog tb.v adders1a.cfg

Alternatively, if the simulator supports precompiling, then we could do:
compile tb.v // creates work.tb:rtl
simulate adders1a.cfg // begins with work.tb:rtl and descends down the
                      // hierarchy using the rules defined in config addres1a

//-----------------------------------------------------------------
// Adders Scenario #1b
// Same simulation, but using multiple libraries instead of views
//-----------------------------------------------------------------

//-----------------------------------------------------------------
// new lib.map file
// maps gates to glib library, and rtl to rlib library
//-----------------------------------------------------------------
`view gates; // forces gates view for glib - unnecessary but illustrates
            // a view declarations as opposed to a mapping
`library glib
  file "/root/projects/proj1/gates/adder.vg";

`view rtl; // forces rtl view for rlib
`library rlib
  file "/root/projects/proj1/vlog/*.v";

//---------------------------------------------------
// This file: /root/projects/proj1/tb/adders1b.cfg
//---------------------------------------------------
config adders1b;
  design work.tb:module;
  default liblist rlib;
  inst tb.top.i2 liblist glib;
endconfig

Invocation: verilog tb.v adders1b.cfg

//-----------------------------------------------------------------
// Adders Scenario #1e (recommended coding style)
// Simulates:
// tb - (/root/projects/proj1/tb/tb.v)
// all other instances - (/root/projects/proj1/vlog directory)
//
// To invoke simulation from the /root/projects/proj1/tb directory:
// (Assuming -f is standardized)
// verilog -f run1_rtl.f
//-----------------------------------------------------------------
//---------------------------------------------------
// This file: /root/projects/proj1/tb/run1_rtl.f
//---------------------------------------------------
tb.v
adders1_rtl.cfg

//---------------------------------------------------
// This file: /root/projects/proj1/tb/adders1_rtl.cfg
//---------------------------------------------------
config adders1_rtl;
  design work.tb:rtl;
  default liblist lib1;
  default viewlist rtl;
endconfig

<p>//=====================================================================

ASIC Design Example

testbench: tb
top instance: tb.asic1
asic1 instances from gates directory: tb.asic1, tb.asic1.blk1, tb.asic1.blk2,
  (synthesized modules) tb.asic1.blk3, tb.asic1.blk4,
asic1 instances from vlog directory: tb.asic1, tb.asic1.blk1, tb.asic1.blk2,
  (RTL modules w/ sub-blocks) tb.asic1.blk3, tb.asic1.blk4,
                                      tb.asic1.blk1.subblk1_1, tb.asic1.blk1.subblk1_2
ASIC Vendor #1 install directory: /root/asics/asic1_install_035
ASIC I/O cells from the directory: <install_dir>/io/ver
ASIC core cells from the directory: <install_dir>/lib/ver
ASIC dsp cells from the library file: <install_dir>/cores/ver/dsp_cores.v
      (only the dsp1, dsp2 and dsp5 modules will be used)
ASIC Vendor #1 environmental variable (c-shell):
      setenv ASIC1DIR /root/asics/asic1_install_035

//-----------------------------------------------
// This file: /root/projects/proj2/tb/tb.v
// testbench module
//-----------------------------------------------
module tb;
  ...
  asic1 asic1 (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj2/vlog/asic1.v
// design top-level module
//-----------------------------------------------
module asic1 (...);
  ...
  blk1 blk1 (...);
  blk2 blk2 (...);
  blk3 blk3 (...);
  blk4 blk4 (...);
  dsp1 dsp1 (...); // from ASIC1 vendor's dsp_cores.v file
  dsp2 dsp2 (...); // from ASIC1 vendor's dsp_cores.v file
  dsp3 dsp3 (...); // from ASIC1 vendor's dsp_cores.v file
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj2/vlog/blk1.v
// same module name and port list as
// the ../gates/blk1.vg module
//-----------------------------------------------
module blk1 (...);
  ...
  subblk1_1 subblk1_1 (...);
  subblk1_2 subblk1_2 (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj2/gates/blk1.vg
// same module name and port list as
// the ../vlog/blk1.v module
//-----------------------------------------------
module blk1 (...);
  ... // Gate-level blk1 code
endmodule

//-----------------------------------------------
// This file: /root/projects/proj2/tb/lib.map
//-----------------------------------------------
`view gates dir "../gates";
`view rtl file "../vlog/*.v";

`library proj2lib
  file "../gates/*.vg",
  file "../vlog/*.v";

include "/root/asics/asic1_install_035/lib.map";

//-----------------------------------------------
// This file: /root/asics/asic1_install_035/lib.map
// Note that this file will likely be provided by the vendor
//-----------------------------------------------
`view gates file "./lib/ver/*.v, file "./io/ver/*.v;
`view core file "./cores/ver/*.v;

`library vendor1_lib
  dir "./lib/ver",
  dir "./io/ver",
  file "./cores/ver/dsp_cores.v",
  viewlist core gates;

//-----------------------------------------------
// This file: /root/projects/proj2/tb/asic1_rtl.cfg
//-----------------------------------------------
config asic1_rtl;
  design work.tb:rtl;
  default liblist proj2lib vendor1_lib;
  default viewlist rtl; // core view picked up from viewlist in vendor's lib.map
endconfig

Invocation: verilog tb.v asic1_rtl.cfg

//-----------------------------------------------
// This file: /root/projects/proj2/tb/asic1_gates.cfg
//-----------------------------------------------
config asic1_rtl;
  design work.tb:rtl;
  default liblist proj2lib vendor1_lib;
  default viewlist gates;
endconfig

Invocation: verilog tb.v asic1_gates.cfg

//=====================================================================

Board design with FPGAs, TTL, company parts, vendor parts example

testbench: tb
top instance: tb.myboard
myfpga1 instances from gates dir: tb.myfpga1a
  (synthesized, placed & routed fpga design)
myfpga1 instances from vlog dir: tb.myfpga1, tb.myfpga1.myblk1_1,
  (RTL modules w/ sub-blocks) tb.myfpga1.myblk1_2, tb.myfpga1.myblk1_3
myfpga2 instances from gates dir: tb.myfpga2
  (synthesized, placed & routed fpga design)
myfpga2 instances from vlog dir: tb.myfpga2a, tb.myfpga2a.myblk2_1,
  (RTL modules w/ sub-blocks) tb.myfpga2a.myblk2_2,
tb.myfpga2a.myblk2_3
                                      tb.myfpga2b, tb.myfpga2b.myblk2_1,
                                      tb.myfpga2b.myblk2_2,
tb.myfpga2b.myblk2_3
FPGA Vendor #1 install directory: /root/fpgas/fpga1_install
FPGA #1 gates from the directory: <fpga1 install_dir>/ver
FPGA #1 UDPs from the file: <fpga1 install_dir>/prim/udps.v
FPGA Vendor #1 environmental variable (c-shell):
      setenv FPGA1DIR /root/fpgas/fpga1_install
FPGA Vendor #2 install directory: /root/fpgas/fpga2_install
FPGA #2 gates from the directory: <fpga2 install_dir>/ver
FPGA #2 UDPs from the file: <fpga2 install_dir>/prim/udps.v
FPGA Vendor #2 environmental variable (c-shell):
      setenv FPGA2DIR /root/fpgas/fpga2_install
asic2 instances from gates dir: tb.asic2
  (synthesized asic2 design)
ASIC Vendor #2 install directory: /root/asics/asic2_install
ASIC core cells from the directory: <asic2 install_dir>/lib/src/vlg
ASIC macro cells from the directory: <asic2 install_dir>/lib/src/macros
ASIC Vendor #2 environmental variable (c-shell):
      setenv ASIC2DIR /root/asics/asic2_install
PXX1 Vendor install directory: /root/company/vendor
PXX1 wrapper file: <vendor install_dir>/vlg/x_pxx1.v
PXX1 functional model file: <vendor install_dir>/vlg/x_pxx1fm.v
PXX1 definitions file: <vendor install_dir>/vlg/x_pxx1df.v
PXX1 Vendor environmental variable (c-shell):
Company TTL library directory: /root/company/library/ttl
Company passive devices directory: /root/company/library/passives
      setenv PXX1DIR /root/company/vendor

//-----------------------------------------------
// This file: /root/projects/proj3/tb/tb.v
// testbench module
//-----------------------------------------------
module tb;
  ...
  myboard myboard (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj3/vlog/myboard.v
// design top-level module
//-----------------------------------------------
module myboard (...);
  ...
  myfpga1 myfpga1a (...);
  myfpga1 myfpga1b (...);
  myfpga2 myfpga2 (...);
  asic2 asic2 (...); // module not shown - module name matches file name
  PXX1 PXX1 (...);
  ls244 u1 (...); // module not shown - module name matches file name
  ls244 u2 (...); // ""
  ls00 u3 (...); // module not shown - module name matches file name
  ls04 u4 (...); // module not shown - module name matches file name
  r r1 (...); // module not shown - module name matches file name
  r r2 (...); // ""
  r r3 (...); // ""
  supply0 gnd1 (...); // module not shown - module name matches file name
  supply0 gnd2 (...); // ""
  supply1 vcc1 (...); // module not shown - module name matches file name
  supply1 vcc2 (...); // ""
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj3/vlog/myfpga1.v
// same module name and port list as
// the ../gates/myfpga1.vg module
//-----------------------------------------------
module myfpga1 (...);
  ...
  // RTL instantiations
  myblk1_1 myblk1_1 (...); module not shown - module name matches file name
  myblk1_2 myblk1_2 (...); module not shown - module name matches file name
  myblk1_3 myblk1_3 (...); module not shown - module name matches file name
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj3/gates/myfpga1.vg
// same module name and port list as
// the ../vlog/myfpga1.v module
//-----------------------------------------------
module myfpga1 (...);
  ... // Gate-level myfpga1 code
endmodule

//-----------------------------------------------
// This file: /root/projects/proj3/vlog/myfpga2.v
// same module name and port list as
// the ../gates/myfpga2.vg module
//-----------------------------------------------
module myfpga2 (...);
  ...
  // RTL instantiations
  myblk2_1 myblk2_1 (...); module not shown - module name matches file name
  myblk2_2 myblk2_2 (...); module not shown - module name matches file name
  myblk2_3 myblk2_3 (...); module not shown - module name matches file name
  ...
endmodule

//-----------------------------------------------
// This file: /root/projects/proj3/gates/myfpga2.vg
// same module name and port list as
// the ../vlog/myfpga2.v module
//-----------------------------------------------
module myfpga2 (...);
  ... // Gate-level myfpga2 code
endmodule

//-----------------------------------------------
// This file: /root/company/vendor/vlg/x_pxx1.v
//-----------------------------------------------
module PXX1 (...);
  ...
  PXX1_def PXX1_def (...);
  PXX1_fm PXX1_fm (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/company/vendor/vlg/x_pxx1df.v
//-----------------------------------------------
module PXX1_def (...);
  ...
endmodule

//-----------------------------------------------
// This file: /root/company/vendor/vlg/x_pxx1fm.v
//-----------------------------------------------
module PXX1_fm (...);
  ...
endmodule

//-----------------------------------------------------------------
// Board Design Scenario #1a (recommended coding style)
//
// To invoke simulation from the /root/projects/proj3/tb directory:
// verilog -f run1.f
//-----------------------------------------------------------------
//-----------------------------------------------
// This file: /root/projects/proj3/tb/lib.map
//-----------------------------------------------
`view gates dir "../gates";
`view rtl file "../vlog/*.v";

`library proj3lib
  file "../gates/*.vg",
  file "../vlog/*.v";

include "/root/fpgas/fpga1_install/lib.map";
include "/root/fpgas/fpga2_install/lib.map";
include "/root/fpgas/asic2_install/lib.map";
include "/root/company/lib.map";

//-----------------------------------------------
// This file: /root/fpgas/fpga1_install/lib.map
// Note that this file will likely be provided by the vendor
//-----------------------------------------------
`view gates file "./ver/*.v", "./prim/udps.v";

`library fpga1lib
  dir "./ver",
  dir "./prim";

//-----------------------------------------------
// This file: /root/fpgas/fpga2_install/lib.map
// Note that this file will likely be provided by the vendor
//-----------------------------------------------
`view gates file "./src/*.v;

`library fpga2lib
  dir "./src";

//-----------------------------------------------
// This file: /root/fpgas/asic2_install/lib.map
// Note that this file will likely be provided by the vendor
//-----------------------------------------------
`view gates file "./lib/src/macros/*.v", dir "./lib/src/vlg";

`library asic2lib
  file "./lib/src/.../*.v";

//-----------------------------------------------
// This file: /root/company/lib.map
//-----------------------------------------------
`view rtl;

`library ttlLib
  dir "./library/ttl";

`library passiveLib
  dir "./library/passives";

`library PXXLib
  file "./vendor/vlg/x_pxx1*.v";

//---------------------------------------------------
// This file: /root/projects/proj3/tb/boardRTL.cfg
//---------------------------------------------------
config boardRTL;
  design work.tb:rtl;
  default liblist proj3lib fpga1lib fpga2lib asic2lib ttlLib passiveLib PXXLib,
          viewlist rtl;
endconfig

//-----------------------------------------------------------------
// Simulation scenario #0
// All RTL models for this simulation configuration
//
// To invoke simulation from the /root/projects/proj3/tb directory:
//-----------------------------------------------------------------
Invocation: verilog tb.v boardRTL.cfg

<p>//-----------------------------------------------------------------
// Simulation scenario #1
// RTL models for most devices, gate-level model
// for the myfpga1b instance
//-----------------------------------------------------------------
//---------------------------------------------------
// This file: /root/projects/proj3/tb/board1.cfg
//---------------------------------------------------
config fpga1gate;
  design proj3lib.myfpga1:gates;
  default liblist proj3list fpga1Lib,
          viewlist gates;
endconfig

config board1;
  design work.tb:rtl;
  default liblist proj3lib fpga1lib fpga2lib asic2lib ttlLib passiveLib PXXLib,
          viewlist rtl;
  path tb.myboard.myfpga1b binding proj3Lib.fpga1gate:config;
endconfig

//-----------------------------------------------------------------
// To invoke simulation from the /root/projects/proj3/tb directory:
//-----------------------------------------------------------------
Invocation: verilog tb.v board1.cfg

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