From: Adam Krolnik (adamk@cyrix.com)
Date: Mon Jan 11 1999 - 12:33:33 PST
[ACK - Updated this proposal with addition
of mandatory level parameter in `line directive.]
B29: Line and File compiler directive.
The C preprocessor (cpp) is the model of the preprocessor that the Verilog
language uses. Currently there are several directives in 'cpp' that are not
present in the Verilog definition. These directives are:
`ifndef `line `if `elif
The directive `ifndef is already accepted for addition. The remainder are the
subject of this proposal. The current proposal asks for the `line directive
this proposal extends this to add `if and `elif.
Justifications:
The line number compiler directive is useful for source to source translators
to reflect original file/line numbers to the compiler for future reference
to the original source code. In order for this information to be useful there
must be a single syntax to accept this information in order to properly
report it.
The `if and `elif compiler directives are proposed for consistency with
the C language preprocessor. They showed use to include in the C definitions
and are useful to extend conditional compilation selection. These additional
directives will simplify complex conditional compilation setup.
Proposal:
Add section 16.7, `line
The line number (`line) compiler directive is used to reset the current line
number of the current file to the arguments presented. This can be used to
reflect the line number and file name of the original file - if the actual
source file has been modified by addition of lines. After specifying
the new line number or file name, the compiler can correctly refer to
the original source file location for example error messages, source code
debugging, etc.
The syntax for the 'line compiler directove is given in Syntax 16-X.
line_compiler_directive ::=
`line number "filename" level
The directive can be specified anywhere within the Verilog HDL source
description. The number is the new line number of the next line. The
filename is the new name of the file. The filename can be a full or
relative path name. If the filename is omitted, only the line number
is updated. The level indicates whether you have entered (value is 1) an
include file, exited (value is 2) an include file or (value is 0) done
neither.
Add section 16.5 `if `elif
These conditional compilation directives are used to include optional lines
of Verilog HDL source description during compilation. The `if compiler
directive evaluates the given expression.
If the expression evaluates to a non-zero value then the following source
code lines are included for compilation. If the expression evaluates to zero
and an `else directive exists then the source code following the `else
directive is included for compilation. The `elif compiler directive
is a shortened form of the two sequential directives `else and `if and
has the same functionality. The `elif compiler directive doesn't require
a `endif directive to close the block but it does require a previous `if
directive.
The expression evaluated by the `if and `elif compiler directives may
include any of the verilog operators (unary, binary, ternary) and the
additional "defined" unary operator. This additional operator provides
the same functionality as the `ifdef compiler directive. This operator
returns zero if the subsequent preprocessor value is not defined with
a value. It returns non-zero if the preprocessor value is defined.
The syntax of the "defined" unary operator is the following:
unary_defined ::= defined preprocessor-symbol
The preprocessor-symbol is a symbol that may or may not have been defined
using the 'define compiler directive.
<p><p><p><p><p> Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
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