From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Jan 12 1999 - 11:09:22 PST
Hello Tom,
Thanks for the time to make the proposal and convert the examples.
Here are my questions/comments.
0. This proposal is huge in the amount of functionality that it presents!
Add to it attributes - I am beginning to get worried about this amount of
functionality added at the last minute without some good thinking about
it. We argued/thought more about the mundane erratta/enhancements than
this one.
1. lib.map syntax
Hate the `view, `library, `this `that `this again!
A. I would rather see the `view (which can be coded into Verilog source
code files) functionality reduced. This seems like a big extension
of `uselib which people don't seem to happy to have.
I would support this functionality in a lib.map (or equivalent)
file. But I don't like keeping the ` marks to start the commands.
It is obtuse to me to have +define and compiler options as part of a view.
B. What does it mean to have a +define with this view?
Does the compiler have to analyze the source files repeatedly
for each view encountered?
C. What does it mean to have a compiler option with a view?
Does the compiler have to optimize the source files differently
for each view encountered?
I can understand the usefulness of having this - the debugging
example. But I think it's too much to be able to put this
all in the source code as a super compiler directive. If its
still kept in how about merging macro and arg into one -
you can say +define+MACRO which is a command line argument.
2. You show examples of an equivalent -y <> -v <> operation in these
files. How does one do the equivalent of +libext for directories?
3. Example Senario 1e (asic1_install_035) How does core view
get incorporated into rtl?
You show an example of including additional elements into the
library definition file. I don't understand the viewlist
functionality. There is a viewlist in the config that
only lists rtl. Why should the core view be searched?
4. What happens if a vendor library defines a view that is
in conflict with a view from another library? Is there
the ability to rename the view?
5. What is the difference between inst and path clauses?
One of them must refer to a instance and the tree of
instances below it.
6. What would you do to read in the lib.map file if it
resides somewhere other than ./ ?
E.g. All examples run verilog from the tb/ directory.
What if you were trying to say
verilog tb/tb.v cfg/adders1b.cfg
7. How about an example where hierarchical config files
are used? E.g.
You have a directory <path_to_old_asic> that contains
a config file defining that ASIC (and maybe a lib.map
file that defines the libraries used.)
You are creating a new board that instantiates that.
You simply want to refer to that configuration file
since it has all the information necessary.
8. Is there a way to specify a lib_cell_view_name for inclusion
in a simulation that is not instantiated? E.g. I have some
design verification modules that are listed in a library.
Is there a way to have some of these compiled into the
simulation or must they be explicitly called out I.e.
<my_path_to_module>/<my_module>.v
9. Can a lib.map file define the default liblist search order?
Your examples show the configuration file defining the search
order. But what if you defined library stuff in lib.map and
wanted to keep all library stuff there - element selection,
order of libraries searched, etc.
10. If you are allowing all lib.map functionality to be specified
as compiler directives in the source - why not also allow
that functionality to be specified in the configuration files?
E.g.
//---------------------------------------------------
// This file: /root/projects/proj1/tb/adders1a.cfg
//---------------------------------------------------
`view gates file ".../*.vg;
`view rtl file ".../*.v;
`library lib1
file "/root/projects/proj1/gates/adder.vg", // gates view
file "../vlog/*.v"; // rtl view
config adders1a;
default liblist lib1,
viewlist rtl;
path tb.top.i2 viewlist gates;
endconfig
<p>11. Section 4.2 Attributes should be typeless.
12. Section 4.4 sounds like 'references' delayed until binding time.
<p><p> Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
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