From: Tom Fitzpatrick (tfitz@cadence.com)
Date: Mon Jan 18 1999 - 10:46:08 PST
BAD MSG:
Hi Kevin,
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You are correct that the Verilog 'view' is equivalent to the VHDL
'architecture'. According to our representative to Verilog-AMS, your
proposal to use the term 'view' in Verilog-AMS was defeated. The term
'view' is NOT part of Verilog-AMS, and is therefore free for us to use in
configurations. Besides, the term 'arch' is a relatively common macro, and
making it a keyword would break existing designs.
Thanks for your input,
-Tom
At 10:47 PM 1/15/99 +0000, Kev wrote:
>Hi again,
>
>Since I received no response to the question about whether
>Verilog 'view' is equivalent to VHDL 'architecture' I'll
>assume that it is.
>
>Assuming so, you should really use 'arch' instead of 'view'
>in your spec. to avoid confusion. "View" was used in the OVI
>Verilog-AMS group for describing the genuinely multi-view
>object in a mixed-signal simulation - i.e.signals on the
>analog/digital boundary, which can have a voltage or current
>value as well as a logic (1,0,X) value.
>
>The original discussion documents are still on-line at:
>
> http://www.dnai.com/~orpheus/lrm/
>
>At the time I also proposed an extension of the multiple
>(signal) view scheme for extending Verilog to support other
>'views' e.g. user defined enums (like VHDL MVL7) and a
>resolution scheme (in order to allow multi-language
>simulation boundaries).
>
>Obviously I'd like to reserve 'view' for that use, since
>using 'view' where 'architecture' would do equally well will
>lead to unnecessary confusion - and I can't think of another
>word other than 'view' to use in the mixed signal boundary
>case.
>
>Regards,
>Kev.
>
>
>Adam Krolnik wrote:
>>
>> A question about all the selection/expansion clauses.
>>
>> What is the difference between
>>
>> cell <cell> bind <lib_cell_name>
>> cell <cell> liblist <lib>:<view>
>>
>> Does liblist apply a new library search list to the named cell
>> and its children?
>>
>> I.e. A library search list of only 1 library should select that exact one.
>>
>> A second (large) question. I made this list and wrote what I thought
>> it meant. Is this correct?
>>
>> Valid Combinations(16) :: Meaning(use)
>>
>> default liblist specify default order of libraries to search
>> default viewlist specify default order of views to search
>> default stoplist specify views to not expand if selected.
>> lib viewlist respecify view order for library.
>> cell liblist specify library list for this cell.
>> cell viewlist specify view list for this cell
>> cell stoplist specify stop list for cells that select these views.
>> cell bind specify specific lib/cell/view for these cells.
>> inst liblist specify library list order for these instances.
>> inst viewlist specify view list order for these instances.
>> inst stoplist specify stop views for these instances.
>> inst bind specify specific lib/cell/view for these instances.
>> path liblist specify library list for this instance and children.
>> path viewlist specify view list for this instance and children.
>> path stoplist specify stop list for this instance and children
>> that select these views
>> path bind specify specific lib/cell/view for this instance.
>>
>> Which of these would you say would be most often used?
>>
>> 1. default liblist
>> 2. default viewlist
>> 3. path viewlist
>> 4. path liblist
>> 5. cell viewlist
>> 6. cell liblist
>> 7. lib viewlist
>
>--
>http://www.v-ms.com
>mailto:admin@v-ms.com Mixed Signal Simulation
>
>
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438
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