From: Kev (kev@v-ms.com)
Date: Tue Jan 19 1999 - 03:23:02 PST
Tom Fitzpatrick wrote:
<p>BAD MSG:
>
Hi Kevin,
>
> You are correct that the Verilog 'view' is equivalent to the VHDL
> 'architecture'. According to our representative to Verilog-AMS, your
> proposal to use the term 'view' in Verilog-AMS was defeated. The term
> 'view' is NOT part of Verilog-AMS, and is therefore free for us to use in
> configurations. Besides, the term 'arch' is a relatively common macro, and
> making it a keyword would break existing designs.
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There was no vote on the use of the word 'view', the vote was about
whether you can see multiple views of a signal in the same context e.g.
have two processes in the same module one (say) contributing current and
another reading the logic value (this sort of thing would happen if you
back annotate a capacitor into your logic and flatten the hierarchy). The
vote was won by Cadence's "single view" scheme - which doesn't allow the
user to specify that kind of module, but both "views" still exist. I
will probably raise the issue again in the IEEE comittees, since there
are major semantic problems with the Cadence Verilog-AMS proposal in this
and other areas.
BTW (since you work in Cycle Simulation), the argument about multiple views
of signals extends to mixing regular Verilog behavior and reduced
representations like those in cycle-based simulators, i.e. where the
Verilog[-D] view of the signal is 0/1/X and strength supply/strong/pull/
weak/highz, the cycle-simulator view is usually 0/1 (without strength).
On the boundary betweeen (say) Verilog-XL and your cycle-based simulator
you will have two views: the V-XL view (say 'Z') and the cycle simulators
view (a corresponding '0' or '1'), although the actual physical signal is
the same.
I'm hoping that if you use "archtecture" instead of "view" it will avoid
confusion when we get around to discussing the two topics at the same time.
I don't really mind if you use 'view' as the keyword in the language
definition, as long as the semantic description makes it clear that it
represents architecture (as in VHDL).
Regards,
Kev.
> Thanks for your input,
> -Tom
>
> At 10:47 PM 1/15/99 +0000, Kev wrote:
> >Hi again,
> >
> >Since I received no response to the question about whether
> >Verilog 'view' is equivalent to VHDL 'architecture' I'll
> >assume that it is.
..
> Senior Technical Marketing Manager Cadence Design Systems, Inc.
> Cycle Simulation Products 270 Billerica Rd.
> Logic Design and Verification Business Unit Chelmsford, MA 01824
> x6438 (978)446-6438
-- http://www.v-ms.com mailto:admin@v-ms.com Mixed Signal Simulation
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