From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Jan 26 1999 - 07:31:45 PST
[ACK-VSG - Specify no effect when `resetall occurrs.
Add language to indicate information changes when
a new file is read and information is stored when
an include file is read/restored when at end of
include file. Is this sufficient?
Do I need to say filename/linenumber is not accessible
by library searching algorithms? I don't understand
what was meant by the question/statement. ]
[ACK - Delete optional filename argument in line directive.
Used compilation_constant_expression for `if directive.
Described use of `endif with `if. {There is no
corresponding discussion of the requirement of `endif
with `ifdef in the current LRM.}
Updated this proposal with addition of mandatory level
parameter in `line directive.
]
B29: Line and File compiler directive.
The C preprocessor (cpp) is the model of the preprocessor that the Verilog
language uses. Currently there are several directives in 'cpp' that are not
present in the Verilog definition. These directives are:
`ifndef `line `if `elif
The directive `ifndef is already accepted for addition. The remainder are the
subject of this proposal. The current proposal asks for the `line directive
this proposal extends this to add `if and `elif.
Justifications:
The line number compiler directive is useful for source to source translators
to reflect original file/line numbers to the compiler for future reference
to the original source code. In order for this information to be useful there
must be a single syntax to accept this information in order to properly
report it.
The `if and `elif compiler directives are proposed for consistency with
the C language preprocessor. They showed use to include in the C definitions
and are useful to extend conditional compilation selection. These additional
directives will simplify complex conditional compilation setup. The
additional operator 'defined' allows testing of preprocessor symbols
within the `if and `elif directives.
Proposal:
Add section 16.7, `line
The compiler is expected to maintain current line and the filename of the
file being compiled. The line number (`line) compiler directive is used
to reset the current line number and filename of the current file to the
arguments presented. This can be used to reflect the location in an
original file - if the actual source file has been modified by
addition or reduction of lines. After specifying the new line number
or file name, the compiler can correctly refer to the original source file
location. For example error messages, source code debugging, etc. can
direct the user to the actual original line.
The syntax for the 'line compiler directive is given in Syntax 16-X.
line_compiler_directive ::=
`line number "filename" level
The directive can be specified anywhere within the Verilog HDL source
description. The number is the new line number of the next line. The
filename is the new name of the file. The filename can be a full or
relative path name. The level indicates whether you have entered
(value is 1) an include file, exited (value is 2) an include file
or (value is 0) have done neither.
The results of this directive are not affected by the compiler directive
`resetall. As the compiler processes the remainder of the file and new
files, this information is updated to the current line number and filename.
When processing include files, it is expected that this information is stored
for later restoration at the termination of the include file.
<p>Add section 16.5 `if `elif
These conditional compilation directives are used to include optional lines
of Verilog HDL source description during compilation. The `if compiler
directive evaluates the given expression. The syntax for the directives is
given in Syntax 16-X.
if_compiler_directive ::=
`if compilation_constant_expression
elif_compiler_directive ::=
`elif compilation_constant_expression
If the compilation_constant_expression evaluates to a non-zero value then
the following source code lines are included for compilation. If the
expression evaluates to zero and an `else directive exists then the
source code following the `else directive is included for
compilation. The `elif compiler directive is a shortened form of the two
sequential directives `else and `if and has the same functionality.
The `elif directive must follow a text region that is controlled by an
`if or an `elif directive. Each `if directive requires a `endif directive to
enclose the text region. It may be after the text region or after the
text region of the corresponding `else or `elif directive. Nested `if
directives do require matching nested `endif directives.
The expression evaluated by the `if and `elif compiler directives may
include any of the verilog operators (unary, binary, ternary) and the
additional "defined" unary operator. This additional operator provides
the same functionality as the `ifdef compiler directive. This operator
returns zero if the subsequent preprocessor value is not defined with
a value. It returns non-zero if the preprocessor value is defined.
The syntax of the "defined" unary operator is the following:
unary_defined ::= defined preprocessor-symbol
The preprocessor-symbol is a symbol that may or may not have been defined
using the 'define compiler directive.
<p><p><p> Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
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