From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Feb 22 1999 - 12:53:50 PST
BAD MSG:
Dear BTF -
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It is time to review the Verilog LRM Draft 2.
We have been assigned the following sections:
2, 3, 4, 6, 9, 10, 11, 12, 13, 16-(shared with the ASIC Task Force), 18, A,
B, C-(shared with the ASIC task Force).
I would like each BTF member to review our assigned sections and provide
feedback. I would also like to assign a lead on each section to do a more
thorough examination of one section and also to be the collector of
feedback from the other BTF members for that section. The lead should also
compile each of the examples in their section to check the model for accuracy.
I will be calling each of you personally on Thursday to request your
participation and make an assignment. If you have a desire to take a
particular section for review, please e-mail me before Thursday. Thanks!
Regards - Cliff Cummings
//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design, Inc. Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
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