Re: Verilog Configuration Goals Requested

From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Feb 23 1999 - 12:33:11 PST


:>11) Different levels of debugging capability is desirable (James Markovitch)

:This is especially where views make a difference. This actually falls most
:naturally into the separate-compile use-model, where I can compile my
:module several times with different options:

This can be very bad.

Tom's proposal states that +args and +define+ command line options
will alter the set of modules selected for a simulation from libraries.
E.g.

Consider a module that uses a `define inside it for debugging - but YOU
don't know that. You may be using this module or, you may be simulating
a gate version (or some other module from another library.)

You decide to use the same preprocessor name for your own stuff. Now you
decide to simulate with it defined. Guess what, you just included that
module using the same `define.

What can result?

1. No compilation - rtl model doesn't plug into gates
2. Incorrect simulation - other module doesn't work in current environment!

This is action at a distance. You didn't explicitly state you wanted modules
to be changed - but you did by setting a preprocessor name!

<p><p> Adam Krolnik
    Verification Engineer
    Cyrix - NSC.
    Richardson TX. 75085



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