From: Stuart Sutherland (stuart@sutherland.com)
Date: Fri Feb 26 1999 - 09:07:46 PST
Here's my opinion:
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After a quick review, I cannot make heads or tails of the current
configuration proposal, or ***ANY*** or the examples. I will not vote in
favor of the current, overly fat proposal. I heartily recommend the BTF
create a VERY simple configuration syntax. Here's is what I think is needed:
1. Standardize `uselib as a basic form of configurations. It's already the
de facto standard, and should be documented. The description of `uselib
can explain the limitations of using compiler directives for configuration
management, and can refer to whatever section contains the new
configuration statements.
2. Provide a new, VERY BASIC form of configurations that is in a separate
file from the Verilog source code. This basic config file should:
- Specify a default virtual library name.
- Specify zero, one or more additional virtual library names.
- Specify physical paths for each virtual library name. For example:
- Specify virtual names for one or more instance scopes of a design.
- Specify actual hierarchical paths for each virtual instance scope.
- Use a `uselib like syntax (it's already familiar) to specify
libraries and library search order. The uselib statements
would use the virtual library and instance scope names. The
library and/or search path specified by the uselib statement
can be different for each virtual instance scope defined.
3. Reserve the configuration keywords from the Cadence proposal, so that
they are illegal as virtual names. This will allow future expansion of the
configuration file.
REMEMBER THE K.I.S.S. PRINCIPAL! (Keep It Simple [for] Stupid -- "stupid"
being me, the guy who has to try to use what the BTF comes up with).
<p>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland.com
Specializing in Verilog HDL consulting and training.
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