From: Kev (kev@v-ms.com)
Date: Fri Feb 26 1999 - 11:25:08 PST
BAD MSG:
To some extent I agree with Stuart on this. While it would be nice to have
omething
better than exists, the current stuff isn't going to go away.
X-Lines: 58
Content-Type: text/plain; charset="us-ascii"
Content-Length: 2453
X-Status: $$$$
X-UID: 0000000845
Status: RO
Also, configuration is the only decent part of VHDL. So to make life simpler for
everyone, I would just add parsing VHDL configurations on top of the `view' (aka
architecture) stuff you are adding.
Kev.
Stuart Sutherland wrote:
> Here's my opinion:
>
> After a quick review, I cannot make heads or tails of the current
> configuration proposal, or ***ANY*** or the examples. I will not vote in
> favor of the current, overly fat proposal. I heartily recommend the BTF
> create a VERY simple configuration syntax. Here's is what I think is needed:
>
> 1. Standardize `uselib as a basic form of configurations. It's already the
> de facto standard, and should be documented. The description of `uselib
> can explain the limitations of using compiler directives for configuration
> management, and can refer to whatever section contains the new
> configuration statements.
>
> 2. Provide a new, VERY BASIC form of configurations that is in a separate
> file from the Verilog source code. This basic config file should:
>
> - Specify a default virtual library name.
>
> - Specify zero, one or more additional virtual library names.
>
> - Specify physical paths for each virtual library name. For example:
>
> - Specify virtual names for one or more instance scopes of a design.
>
> - Specify actual hierarchical paths for each virtual instance scope.
>
> - Use a `uselib like syntax (it's already familiar) to specify
> libraries and library search order. The uselib statements
> would use the virtual library and instance scope names. The
> library and/or search path specified by the uselib statement
> can be different for each virtual instance scope defined.
>
> 3. Reserve the configuration keywords from the Cadence proposal, so that
> they are illegal as virtual names. This will allow future expansion of the
> configuration file.
>
> REMEMBER THE K.I.S.S. PRINCIPAL! (Keep It Simple [for] Stupid -- "stupid"
> being me, the guy who has to try to use what the BTF comes up with).
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
>
> www.sutherland.com
>
> Specializing in Verilog HDL consulting and training.
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:26 PDT
and
sponsored by Boyd Technology, Inc.