From: Tom Fitzpatrick (tfitz@cadence.com)
Date: Thu Apr 01 1999 - 06:35:37 PST
BAD MSG:
Hi James,
ontent-Length: 22872
X-Lines: 670
X-Status: $$$$
X-UID: 0000000856
Status: RO
I guess you're not on the BTF reflector. I've already sent out the attached
proposal to the BTF, and I'm just waiting on the scheduling of the next BTF
call.
Thanks,
-Tom
PS. I've also attached another proposal to address the synthesis pragma
issue with a more general solution.
At 05:31 PM 3/31/99 -0800, James A. Markevitch wrote:
>I was stuck on the East Coast and couldn't attend the telecon for the 3/1
>meeting on configurations, and I haven't seen anything mailed out since
>that meeting? What was the outcome from that meeting and is there anything
>new to comment on?
>
>Thanks,
>
>James Markevitch
>jam@magic.com
>
>
>
Attachment Converted: "E:\INCOMING\configs_lib_only1.pdf"
Attachment Converted: "E:\INCOMING\AttributesProposal1.PDF"
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
RTL Verification Flow/Product Engineering 270 Billerica Rd.
Design and Verification R&D Chelmsford, MA 01824
x6438 (978)446-6438From ???@??? Mon Apr 12 15:23:51 1999
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Message-ID: <37126FA5.6F9AC577@americasm01.nt.com>
Date: Mon, 12 Apr 1999 18:11:49 -0400
From: "Anders Nordstrom" <andersn@nortelnetworks.com>
Reply-To: "Anders Nordstrom" <andersn@nortelnetworks.com>
Organization: Nortel Networks
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<BODY TEXT="#000000" BGCOLOR="#FFFFFF" LINK="#0000FF" VLINK="#FF0000" ALINK="#000088">
Team,
Below is a list of all our outstanding enhancements and errata to date
as well as
<BR>who is working on them.
<UL>
<LI>
B05 Configurations</LI>
<LI>
B11 proposal ready for vote - Anders</LI>
<LI>
B13 Adam to update proposal</LI>
<LI>
B22 Waiting for letter from Cadence - Tom</LI>
<LI>
B29</LI>
<LI>
B31</LI>
<LI>
B35</LI>
<LI>
B36 Mac is writing proposal</LI>
<LI>
B37 Mac is writing proposal</LI>
<LI>
B38 new item (enclosed)</LI>
</UL>
<UL>
<LI>
BE1, 40, 49, 68 and 69 Cliff is working on new BNF</LI>
<LI>
BE71 Stefen is writing proposal</LI>
<LI>
BE72 Stefen is writing proposal</LI>
<LI>
BE79 proposal ready for vote - Anders</LI>
<LI>
BE81</LI>
</UL>
<BR>Please try to send out proposals by April 16 so that we can vote
on them on the April 19 conference call.
Regards,
Anders
<PRE>--
+-------------------------------------------------------------------------+
| Anders Nordstrom |
| Manager OC192 Data ASIC Development |
| |
| Nortel Networks Email: andersn@nortelnetworks.com |
| P.O. Box 3511 Station C Phone: 613-763-9186 |
| Ottawa, Ontario K1Y 4H7 Fax: 613-763-2626 |
+-------------------------------------------------------------------------+</PRE>
</BODY>
</HTML>
</x-html><x-html><HTML>
<HEAD>
<TITLE> B38 </TITLE>
</HEAD>
<BODY BGCOLOR="#FFFFFF">
<BR>
<HR SIZE=5 NOSHADE>
<H2> B38 - Verilog Annotations (pragmas) </H2>
<TABLE BORDER COLS=2 WIDTH="75%" >
<TR><TD>
Section: </TD><TD> TBD
</TD></TR><TR><TD>
Date Submitted: </TD><TD> 990223
</TD></TR><TR><TD>
Requestor: </TD><TD> Tom Fitzpatrick (tfitz@cadence.com)
</TD></TR><TR><TD>
Status: </TD><TD> Submitted
</TD></TR><TR><TD>
Analyzed by: </TD><TD> TBD
</TD></TR><TR><TD>
Synthesizable: </TD><TD> Yes
</TD></TR>
</TABLE>
<H3> Details </H3>
As a member of the 1364 Standards group (Behavioral Task Force), I have
made the following proposal to include "attributes" in Verilog, which could
easily be used to specify pragma information to synthesis tools. The basic
premise of attributes is that they contain embedded information in the
source code which can be used to specify tool-specific information - such
as pragmas, configuration information, cycle-based information, etc - but
that does not affect the simulation behavior of the model. Synthesis
pragmas such as parallel_case and full_case are classic examples of this
type of information, and there seems to be support for coming up with a
mechanism other than comments to specify this data.
Below is the BNF for this proposal. I have spoken with Bhasker, and he has
graciously offered some time during the pragma discussion of your
conference call today for me to discuss this proposal with you. There are
essentially two related issues that need to be resolved separately:
<PRE>
1) What are the synthesis pragmas that need to be specified?
2) What is the syntactic mechanism for specifying them?
</PRE>
This proposal addresses the second question, leaving the first question for
you to decide.
Here is the proposal. Your comments and questions are welcomed.
Thanks, <BR>
-Tom
<PRE>
module top(b,c);
output b;
reg clk,a;
wire b,c;
// instantiate a vhdl module here:
vhdlmod vhdlmod(clk,a,b);
// instantiate a cycle-sim module here:
cyclemod (* cycle = 1; *) cyclemod(clk,a,c);
endmodule
module vhdlmod(clk,a,b) (* foreign = "VHDL WORKLIB.E:a"; *);
input clk,a;
output b;
...
endmodule
</PRE>
Please note that the '(* - *)' syntax was chosen because it is a lexical
token pair that is not currently used in the Verilog language.
<PRE>
Here's the BNF:
This is what an attribute is:
<instance_attr> ::= (* <attr_list> *)
<attr_list>::
::= <attr><,attr>*
<attr>
::= <attr_spec_list>;
<attr_spec_list>
::= <attr_spec><,attr_spec>*
<attr_spec>
::= <attr_name> = <value>
||= <attr_name>
<value>
::= <constant>
||= <constant_expression>
This is how an attribute is used:
variable instances:
<type><range>?<instance_attr><instances>+
<type>
::= REG
||= TIME
||= INTEGER
||= INPUT
||= OUTPUT
||= INOUT
REAL <instance_attr>?<instances>+
REALTIME <instance_attr>?<instances>+
EVENT <instance_attr>?<events>+
<net_type><strength>?<expandrange>?<delay>?<instance_attr>?<net_expression>;
<net_expression>
::= <net_name>
||= <net_name> = <expression>
gate and switch instances:
<gate_type> [<drive_strength>] [<delay>] [<instance_attr>]
<gate_instance>+;
module and udp declarations and instantiations:
MODULE <module_name> [<port_list>] [<instance_attr>];
[<module_item>]
ENDMODULE
PRIMITIVE <prim_name> ((port_list) [<instance_attr>];
<prim_declaration>+
[<prim_initialization>]
<table_definition>
ENDPRIMITIVE
Module or udp ports:
<port_type> [<range>] [<instance_attr>] <list_of_variables>;
<port_type> ::= INPUT
||= OUTPUT
||= INOUT
Function and Task declarations and invocations:
FUNCTION [<range>] <function_name> [<instance_attr>];
<tf_declarations>+
[<statement>]
ENDFUNCTION
TASK <task_name> [<instance_attr>] ;
<tf_declarations>+
[<statement>]
ENDTASK
built-in operators:
<unary_op> [<instance_attr>] <expression>
<expression> <binary_op> [<instance_attr>] <expression>
? [<instance_attr>] <expression> : <expression>
The BNF could be extended to include case/x/z statements as follows:
case_statement ::=
case ( expression ) [<instance_attr>] case_item { case_item } endcase
| casez ( expression ) [<instance_attr>] case_item { case_item } endcase
| casex ( expression ) [<instance_attr>] case_item { case_item } endcase
case_item ::=
expression { , expression } [<instance_attr>] : statement_or_null
| default [<instance_attr>] [ : ] statement_or_null
This would allow a case statement to look something like this:
case (state) (* parallel_case, full_case; *)
1'b0: <statement>;
1'b1: <another_statement>
endcase
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438
</PRE>
This issue was discussed at the 1364.1 RTL synthesis sub committee
meeting on April 6, 1999.
The proposed syntax would apply to annotations that can be attached
to a certain object. <BR>
Translate off / on may be handled using `ifdef if the synthesis
tool were to define for example "rtl_syntesis".
Anders
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Message-ID: <37126AB4.EA89ACCD@americasm01.nt.com>
Date: Mon, 12 Apr 1999 17:50:44 -0400
From: "Anders Nordstrom" <andersn@nortelnetworks.com>
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Team,
I have set up a conference call so that we can continue our discussion
on Configurations
<BR>and to work through the open errata and enhancements.
<BR>I will send out a separate email with the open items.
<BR>
<UL>
<LI>
Date: Monday April 19, 1999</LI>
<LI>
Time: 9:00 am - 12:00 pm PDT (12:00 - 3:00 pm EDT)</LI>
<LI>
Phone: 613-763-6338</LI>
<LI>
passcode: 185505#</LI>
</UL>
<H1>
Agenda</H1>
9:00 - 10:00 Configurations
<BR>10:00 -
Open errata and enhancements.
<BR>
Vote on B11 and BE79 proposals that are attached.<BR>
Vote on other proposals.
Regards,
<BR>
<BR>
Anders
<PRE>--
+-------------------------------------------------------------------------+
| Anders Nordstrom |
| Manager OC192 Data ASIC Development |
| |
| Nortel Networks Email: andersn@nortelnetworks.com |
| P.O. Box 3511 Station C Phone: 613-763-9186 |
| Ottawa, Ontario K1Y 4H7 Fax: 613-763-2626 |
+-------------------------------------------------------------------------+</PRE>
</BODY>
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</x-html><x-html><HTML>
<HEAD>
<TITLE> B11 </TITLE>
</HEAD>
<BODY BGCOLOR="#FFFFFF">
<BR>
<HR SIZE=5 NOSHADE>
<H2> B11 - Automatic width extension beyond 32 bits </H2>
<TABLE BORDER COLS=2 WIDTH="75%" >
<TR><TD>
Section: </TD><TD> 2.5.1 page 7
</TD></TR><TR><TD>
Date Submitted: </TD><TD> 970319
</TD></TR><TR><TD>
Requestor: </TD><TD> adamk@cyrix.com (Adam Krolnik)
</TD></TR><TR><TD>
Status: </TD><TD> proposal
</TD></TR><TR><TD>
Analyzed by: </TD><TD> BTF team and Anders Nordstrom
</TD></TR><TR><TD>
Synthesizable: </TD><TD> Yes
</TD></TR>
</TABLE>
<H3> Details </H3>
Width extension.
If you want to size a constant you need to specify a width to it. E.g. 7'h2 <BR>
If you don't specify a size ('h123) it has a machine word width (I.e. 32 <BR>
bits.) This causes the following statements to provide unexpected behavior:
<PRE>
reg[63:0] a;
initial a = 'h0;
reg[63:0] b;
initial b = 'bz;
</PRE>
Rather, the unsized constant should be extended (signed?, zero?, last-bit?)<BR>
to the width of the lhs. In the example, 'a' should have the value 64'h0, <BR>
not {32'bx, 32'b0}.
<p>>From cliffc@europa.com Fri May 2 11:41:32 1997
I could support this request.
I always find it amusing to run the following code through Synopsys, only to
<BR> find 32 tri-state drivers and 32 and gates with one input tied low.
<PRE>
module driver (y, a, en);
output [63:0] y;
input [63:0] a;
input en;
assign y = en ? a : 'bz;
endmodule
</PRE>
Note: This could potentially break exiting models if anyone has been <BR>
counting on zero-extension for busses greater that 32 bits wide, but it <BR>
seems like an extremely risky strategy to intentionally employ that coding
style.
Regards - Cliff Cummings
From: mac@silicon-sorcery.com
Not unreasonable; the current behavior is not really serving <BR>
any useful purpose, except to confuse newbies.
I would support this proposal. one would need to consider the <BR>
size of unsized constants in expression context:
<PRE>
wire [24:0] a, b;
assign a = (b + 'h23)>>2;
</PRE>
<H3> Proposal </H3>
Add the following sentence at the end of the first paragraph
on page 7 in the 1995 LRM or after the third paragraph on page
9 in Draft 2: <P>
"Unsized unsigned constants where the high order bit is unknown (X or x)
or tri-state (Z or z) are extended indefinitely"
Add to the "Automatic left padding" example on page 8 (10): <BR>
<PRE>
reg [84:0] e, f, g;
e = 'h5; // yields {82{1'b0},3'b101}
f = 'hx; // yields {85{1'hx}}
g = 'hz; // yields {85{1'hz}}
</PRE>
<HR SIZE=5 NOSHADE>
</BODY>
</HTML>
</x-html><x-html><HTML>
<HEAD>
<TITLE> BE79 </TITLE>
</HEAD>
<BODY BGCOLOR="#FFFFFF">
<BR>
<HR SIZE=5 NOSHADE>
<H2> BE79 - Draft 1 Errata - related to B19 </H2>
<TABLE BORDER COLS=2 WIDTH="75%" >
<TR><TD>
Section: </TD><TD> 2.5.1 & 4.1.12
</TD></TR><TR><TD>
Date Submitted: </TD><TD> 981117
</TD></TR><TR><TD>
Requestor: </TD><TD> Tom Fitzpatrick (tfitz@cadence.com)
</TD></TR><TR><TD>
Status: </TD><TD> Proposal
</TD></TR><TR><TD>
Analyzed by: </TD><TD> Tom Fitzpatrick / Anders Nordstrom
</TD></TR>
</TABLE>
<H3> Details </H3>
Section: 2.5.1 <BR>
Page: 8 in 1995 LRM <BR>
Page: 10 in Draft 2
Note 1 should be changed to read: <BR>
"Sized negative constant numbers and sized signed cnstant numbers are
sign-extended when
assigned to a register data type, regardless of whether the register itself
is signed or not."
-Tom
Note from BTF call: Should there be any reference to a negative number?
<PRE>
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438
</PRE>
<H3> Proposal </H3>
Change Note 1 on page 10 in Draft 2 to read:
"Sized negative constant numbers and sized signed cnstant numbers are
sign-extended when
assigned to a register data type, regardless of whether the register itself
is signed or not."
<HR SIZE=5 NOSHADE>
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To: btf@boyd.com
From: Tom Fitzpatrick <tfitz@cadence.com>
Subject: Generated instance question
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Hi Gang,
When using generated instances, is it legal to use a variable for the
instance index in a hierarchical reference? The Proposal only states that
instances can be referenced by f[0], f[1], f[2] and f[3], respectively.
module top;
integer j;
wire[3:0] b;
reg [3:0] a,c[0:3];
genvar i;
generate for (i = 0; i < 4; i = i+1)
foo f(a[i],b[i]);
endgenerate
initial begin
for(j = 0; j < 4; j = j+1)
c[j] = f[j].bar; // can you iterate through generated instances?
end
// or do I have to say:
// c[0] = f[0].bar;
// c[1] = f[1].bar;
// c[2] = f[2].bar;
// c[3] = f[3].bar;
endmodule
module foo(a,b);
input [3:0] a;
output [3:0] b;
reg [3:0] bar;
...
endmodule
<p>Thanks,
-t
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
RTL Verification Flow/Product Engineering 270 Billerica Rd.
Design and Verification R&D Chelmsford, MA 01824
x6438 (978)446-6438
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