From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed May 05 1999 - 17:10:43 PDT
BTF Minutes - 05/04/99 - 9:00 AM-10:30 PM PST
X-Lines: 94
Content-Type: text/plain; charset="us-ascii"
Content-Length: 3463
X-Status: $$$$
X-UID: 0000000892
Status: RO
Attendees: Cliff Cummings, Tom Fitzpatrick, Adam Krolnik,
Next BTF phone conference set for Monday, May 10th.
We decided to spend the entire conference call dedicated to completing the
configuration proposal.
B05 - Configurations
There is no default timescale in Verilog. A module with a missing timescale
is at risk of inheriting an invalid timescale from a previously compiled
module.
Where the LRM talks about delays, add a recommendation to add a `timescale
in front of every module, similarly add a `resetall at the end of every
module to insure that timescales are not inherited by subsequent modules.
This will help identify modules with missing timescales that might cause
simulation timing problems.
Problem: if two modules from different libraries have a `include, there is
no mechanism to specify what directory the include file comes from (the
problem exists if two include files in two different revs of an ASIC
library have the same name and both revs are being used). Tom will add an
incdir option to the BNF statement:
1.1 -
library library_identifier [file_path_spec [{,file_path_spec} [-incdir
file_path_spec [{file_path_spec}]] ]] ;
2.1 - file_path_spec = file_path (without quotes)
2.1 - We need some wording help with the "..." wildcard!! - Tree directory
wild card
2.1.1 - Problems with default libraries - default libraries were removed -
same thing can be accomplished much safer using
library library_identifier *
2.1.1 - multiple modules with the same name are mapped to the same library
in a single invocation of the compiler, then a warning message shall be
issued.
3.1 - change BNF - expand all possibilities of selection_clause and
expansion_clause and then remove the selection_clause and expansion_clause
BNF terms.
Expand descriptions in the text.
3.1.3 - What does everyone think about "inst" vs. "instance" for the
Verilog keyword??
3.1.6 & 3.2 - What does everyone think about "binding" vs. "binds_to" vs.
"use" for the Verilog keyword??
3.2 - Question - can one hierarchically override a config item from a
higher-level config? Do we want to permit this??
5.0 - Remove quotes
5.1 - Remove "and view"
7.0 - Libray misspell corrected
7.1 - Should command line switches be added to the Verilog LRM? Add -L
suggestion to the LRM to permit debate.
7.2 & 7.3 - specify the starting directory for each of these examples.
Automatic tasks - clarify the proposal that variables go away at the end of
the task.
What does it mean to have a nonblocking assignment on the output of a task.
Additional generate comments from Cadence
- for-loop syntax - explicitly require the genvar variable when referencing
instance names.
genvar i;
Require foo f[i] (not foo f)
Only want index variables of the form i=i+1 (not i=i+2, etc.) - (In VHDL,
is this possible?)
Generated instance names are literal names?
Regards - Cliff Cummings
//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design, Inc. Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:27 PDT
and
sponsored by Boyd Technology, Inc.