From: Adam Krolnik (adamk@cyrix.com)
Date: Mon Jun 07 1999 - 11:04:26 PDT
Here is a verilog program that outputs different things
based on the simulator used.
module test;
task f;
output b;
begin
b = 1; disable f;
end
endtask
reg a;
initial begin
f(a);
$display("A is %0d", a);
end
endmodule
<p>XL reports 'A is 1'
VCS reports 'A is x'
VCS (Mac says its a legacy bug they never fixed) should complete
the assignment.
<p> Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
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