From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Jun 08 1999 - 17:12:39 PDT
BAD MSG:
Karen and Tom -
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Could you remind me concerning the arguments against parameterized widths
on literal numbers?
As I recall, you both had arguments against this proposal based on
difficulty parsing the parameter followed by a ' or perhaps your opposition
had something to do with this enhancement making it possible to include
expressions at part of a literal number?
Stu makes some interesting points. Some I agree with and some I don't.
1st - "This is not clean, self-documenting code" - I disagree. I have been
using this coding style for synthesizable parameterized models for years,
so to me it looks fine. SIZE'bz might be a little easier to understand but
this also looks pretty strange to me.
2nd - Stu claims that this coding style is inefficient on interpreted
Verilog simulators. The benchmarks that I ran showed no performance
difference on VCS and only a 3% difference using ModelSim when using
unrealistically high switching activity in my benchmark testbench. Granted
these are both compiled code simulators but that's all I have access to at
this time. All of my benchamark files are attached below for your perusal
and experimentation.
Could you both comment on your objections to this enhancement proposal and
copy Stu?
Regards - Cliff
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>Date: Mon, 10 May 1999 08:59:31 -0700
>To: Adam Krolnik <adamk@cyrix.com>
>From: Stuart Sutherland <stuart@sutherland.com>
>Subject: Re: Enhancement request (parameterized widths)
>Cc: btf@boyd.com
>Sender: owner-btf@boyd.com
>
>BTF,
>
>For my records, can you please point me to the BTF number for enhancement
>request for "parameterized literal number widths", or whatever the proper
>term is? I'm not sure how the BTF works, but on the PTF, we assign a
>number to each and every request, and record our task force decision. If a
>request is rejected, we document why.
>
>I do not find the two e-mail responses for rejecting my enhancement request
>to be satisfactory alternatives.
>
>Cliff's states that parameterized widths can be accomplished using the
>replicate operator, such as:
>
> assign out = en? in: {N{1'bz}};
>
>This is not clean, self-documenting code. It is not run-time efficient for
>interpretive simulators. Using additional operators just to establish a
>vector width goes against the general idea of simplicity and brevity that
>are a strength of Verilog. Finally, using additional operators to
>establish vector widths would be a real mess in a complex, compound
>expression involving several sized operands.
>
>Adam states that the automatic extension proposal will take of the need for
>parameterized widths, but automatic extension is problematic, at best.
>Adam's example is:
>
> assign out = en? in: 'hz; //literal sized to width of lhs
>
>This context-determined width might solve the need for parameterized widths
>IN THIS CONTEXT, but it does not explain how the width would be determined
>in other contexts. For example, what is the width extension for:
>
> reg [N-1:0] RDDATA;
> if (RDDATA[7:0] === 'hx)
>
> Current Verilog behavior extends RDDATA[7:0] to 32 bits, left extending
> with zero, and extends 'hx to 32 bits, left extending with X.
> This is the long-established and well-defined behavior of the
> language. What will the proposed new extension rules do?
>
>And what about:
>
> reg [N-1:0] Y;
> reg [3:0] A;
> assign Y = ({A * -'h3}) << 2;
>
> I'll let you figure out what the current Verilog rules would do. The
> width of 'h3 and 2 will affect the result of the math operations, and
> The concatenate operator has an affect on the current expansion rules.
>
>My point is, an un-defined width is not good coding style. The code is not
>self-documenting, and it may not be obvious as to what the
>context-determined width should be.
>
>I maintain that my enhancement request for parameterized literal widths is
>necessary to make Verilog module instances more configurable on a per
>instance basis.
>
>As this is a formal enhancement request, I expect it to be assigned a BTF
>enhancement number (if it is not specifically part of an existing
>enhancement), and that the BTF will document the result and reasoning of
>its decisions.
>
>Thanks,
>
>Stu
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>Stuart Sutherland Sutherland HDL Inc.
>stuart@sutherland.com 22805 SW 92nd Place
>phone: 503-692-0898 Tualatin, OR 97062
Benchmark files:
::::::::::::::
nonreplicate1.v
::::::::::::::
module nonreplicate1 (y, a, en);
parameter SIZE = 32;
output [SIZE-1:0] y;
input [SIZE-1:0] a;
input en;
assign y = en ? a : 32'bz;
endmodule
::::::::::::::
replicate1.v
::::::::::::::
module replicate1 (y, a, en);
parameter SIZE = 32;
output [SIZE-1:0] y;
input [SIZE-1:0] a;
input en;
assign y = en ? a : {SIZE{1'bz}};
endmodule
::::::::::::::
tb.v
::::::::::::::
`ifdef ICNT
`else
`define ICNT 10_000_000
`endif
`define cycle 100
`timescale 1ns / 1ns
module tb;
wire [31:0] y;
reg [31:0] a;
reg en;
reg clk;
integer i;
parameter half_cycle1 = `cycle/2;
parameter half_cycle2 = `cycle - half_cycle1;
initial begin
clk = 1'b0;
forever begin
#(half_cycle1) clk = 1'b1; // clk high
#(half_cycle2) clk = 1'b0; // clk low
end
end
`ifdef REPLICATE
replicate1 u1 (y, a, en);
`endif
`ifdef NONREPLICATE
nonreplicate1 u1 (y, a, en);
`endif
initial begin
a=8'h00; en = 1;
for (i=0; i<`ICNT; i=i+1) begin
@(posedge clk) en = 1'b0;
@(posedge clk) a = ~a;
en = 1'b1;
end
`ifdef RUN
@(negedge clk) $finish(2);
`else
@(negedge clk) $stop(2);
`endif
end
endmodule
::::::::::::::
non.f
::::::::::::::
tb.v
nonreplicate1.v
+define+NONREPLICATE
+define+RUN
::::::::::::::
rep.f
::::::::::::::
tb.v
replicate1.v
+define+REPLICATE
+define+RUN
::::::::::::::
run.mt
::::::::::::::
#! /bin/sh
ICNT=1_000_000
#ICNT=100
vlib work
vlog -f rep.f +define+ICNT="$ICNT"
/bin/time vsim -c -do 'run -all' tb > ../logs/replicate_mt.log
vlog -f non.f +define+ICNT="$ICNT"
/bin/time vsim -c -do 'run -all' tb > ../logs/nonreplicate_mt.log
::::::::::::::
run.vcs
::::::::::::::
#! /bin/sh
#ICNT=100_000
#ICNT=1000
vcs -f rep.f -o rep.vcs
/bin/time rep.vcs > ../logs/replicate_vcs.log
vcs -f non.f -o non.vcs
/bin/time rep.vcs > ../logs/nonreplicate_vcs.log
<p><p><p>//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design, Inc. Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
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