From: Kevin Cameron (dkc@grfx.com)
Date: Wed Jul 21 1999 - 02:58:32 PDT
> I will say the sensible things to do is to not allow the use
> of specparam outside the specify block. I heard that the IEEE
> standard is allowing this feature, which I believe is wrong. I realize
> that there are some cell libraries from a major vendor in US that
> use this "feature", but the sole purpose of a committe is to
> set up a sensible standard, define the meaning of the standard,
> and get rid of all confusion that may arise due to poor
> specification and implementation in the past.
...
I agree with Tan. There were a bunch of proposed extensions from
Cadence for Verilog-A that appeared without a proper discussion
of what problem they were supposed to solve and with very little
consideration for compatibility with Verilog, this looks like one
of them.
Kev.
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