From: Michael McNamara (mac@surefirev.com)
Date: Wed Jul 21 1999 - 11:15:55 PDT
Ted Elkind writes:
> Hi Stu,
>
> In case no one replied yet, specparams cannot be accessed with bit or
> part selects. They can only provide time or delay values or mtm
> triples. However, they can always appear anywhere in a time or delay
> expression. They cannot appear outside that context. Hence, this is
> legal:
>
> specparam x = 5:6;7;
> ...
> #x Q = DAT;
>
> But this is not:
>
> specparam x = 5:6;7;
> reg y;
> reg [7:0] z;
> ...
> y = z[x];
>
> And neither is this:
>
> specparam [7:0] x = 5:6:7;
>
> Ted
It is interesting that you state that later two usages are illegal.
VCS agrees with you about the illegality, but both Verilog-XL and NC
verilog accept everything you say is illegal.
Consider:
module xx;
specify
specparam[0:3] A = 3:4:5 ;
endspecify
wire [3:0] W1 = {A[3],A[2],A[1],A[0]} ;
initial begin
$display( "A= %b", A ) ;
#10
$display( "W1= %b", W1 ) ;
end
endmodule
Worse, customers using our coverage tools have reported that vendor
libraries are using specparams in many ways that the 1364
specification, and you say are illegal.
Since NC and Verilog-XL accept these usages, venders are doing it, and
hence the rest of the industry gets pushed to support it.
*sigh*
-mac
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