From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Jul 22 1999 - 07:50:33 PDT
Good morning:
<p>One comment about this feature proposal:
There was a simulator language named Endot (N.) created by the
developers of
(now) ModelTech VHDL simulator.
Their language was a HDL simulation language but focused a little more
at a higher level than verilog (No gate primitives, no 'nets' only
register
types.
They had the concept of 'sizing' constants and expressions. For their
language, it was an operator - 'ext' and 'sxt'. The syntax was
12 ext 5 ::= 5'h12
12 sxt 4 ::= -4'd3
<p><p> Adam Krolnik
Verification Lead
LSI Logic
Plano TX
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