From: Steven Sharp (sharp@cadence.com)
Date: Mon Jul 26 1999 - 12:15:26 PDT
I checked with one of our AMS people. They just pointed me at section 3.9.2
of the Verilog standard on conversions, and indicated that they felt it covered
the conversion situation.
They also indicated that they were planning on allowing old-style parameter
declarations with the type determined by the right hand side. They thought
that the standard would end up getting modified to match.
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