From: Ted Elkind (elkind@cadence.com)
Date: Tue Jul 27 1999 - 23:55:56 PDT
No significance should be attached to VXL's failure to enforce proper
syntax. My guess is that bit ranges in specparam declarations are
ignored. VXL is also very sloppy in drawing a distinction between
parameters and specparams. This means that this example from you
contains both illegal syntax and semantics:
module top ;
wire WT = test.A ; // Illegal reference to specparam
endmodule
module test ;
<p> specify
specparam[0:2] A = 3:4:5 ; // Illegal bit-spec in specparam declaration
endspecify
initial
$display( "A= %d", A ) ; // Illegal reference to specparam
wire W1 = A ; // Illegal reference to specparam
endmodule
The new specparam behavior permits specparams outside specify blocks,
but only in timing contexts.
Ted
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