From: Ted Elkind (elkind@cadence.com)
Date: Wed Jul 28 1999 - 00:17:20 PDT
Michael McNamara writes:
> It is interesting that you state that later two usages are illegal.
>
> VCS agrees with you about the illegality, but both Verilog-XL and NC
> verilog accept everything you say is illegal.
>
> Consider:
>
> module xx;
> specify
> specparam[0:3] A = 3:4:5 ;
> endspecify
>
> wire [3:0] W1 = {A[3],A[2],A[1],A[0]} ;
>
> initial begin
> $display( "A= %b", A ) ;
> #10
> $display( "W1= %b", W1 ) ;
> end
>
>
> endmodule
>
> Worse, customers using our coverage tools have reported that vendor
> libraries are using specparams in many ways that the 1364
> specification, and you say are illegal.
>
> Since NC and Verilog-XL accept these usages, venders are doing it, and
> hence the rest of the industry gets pushed to support it.
VXL is sloppy on enforcement of some things, but "A[3]" is a real
eye-opener. Your assessment is right. I'll let Steve Wadsworth
decide what to do as I'm all tied up.
Ted
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:29 PDT
and
sponsored by Boyd Technology, Inc.