From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Aug 18 1999 - 07:27:01 PDT
Good morning Mac, Steve:
<p>>The proponent of constant fuctions cited an example with a triangular
>array; it is certainly possible to come up with weird corner cases;
>but for those I say the designer should use perl to generate the wierd
>verilog.
Maybe, instead of all the generate and constant function constructs
being defined, one define a way for a user to define an additional
preprocessor for all verilog code read in to be passed through.
This would aid the many people who write source to source
translators and now have to write out extra files and instruct
the verilog compilers to compile this alternate verilog source.
If you implement `MIN, `MAX, why limit it to 2 values. It's just as easy
to understand `MAX(3,4,5) vs `MAX(3,`MAX(4,5))
<p><p> Adam Krolnik
Verification Engineer
LSI Logic
Plano TX.
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