From: Steven Sharp (sharp@cadence.com)
Date: Fri Aug 20 1999 - 12:33:13 PDT
I have a question for the hardware designers out there. How much simulation
speed would you be willing to give up to get a simulator that supports the
proposed 1999 enhancements? Information for specific features would be most
useful, but an overall estimate would still help.
If we implemented the enhancements in NC-Verilog, the engineers doing the
work would have to be pulled off of optimization. It would be useful to
know the relative value you place on each.
Steven Sharp
sharp@cadence.com
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