From: Alec Stanculescu (alec@fintronic.com)
Date: Wed Aug 25 1999 - 10:33:04 PDT
A feature that will prove to both slowdown compilation/elaboration
and introduce several specification contradictions is the "Generate"
construct.
The definition of Generate in the context of parameter overrides and their
peculiar usage in Verilog (e.g. erroneous default values of parameters
must not be reported unless the parameters are actually used with
those values) has not been fully thought through in my opinion.
Alec Stanculescu
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:29 PDT
and
sponsored by Boyd Technology, Inc.