From: Michael McNamara (mac@surefirev.com)
Date: Wed Aug 25 1999 - 15:36:14 PDT
Alec Stanculescu writes:
> A feature that will prove to both slowdown compilation/elaboration
> and introduce several specification contradictions is the "Generate"
> construct.
>
> The definition of Generate in the context of parameter overrides and their
> peculiar usage in Verilog (e.g. erroneous default values of parameters
> must not be reported unless the parameters are actually used with
> those values) has not been fully thought through in my opinion.
>
> Alec Stanculescu
Is it truly a slowdown?
Presumably folks are already doing this by some other means (tedious
typing, perl scripts, cut and paste...). Having the compiler spend 300 ms
processing a bit of code like
generate
for(i=0, i < 10; i = i + 1) begin
foo f (clk, a[i], b[9-i], reset, c[i]);
end
endgenerate
has to be better than that...
I do agree that we need to be sure the generate actually will
work, and I applaud any effort by Fintronic and/ or Cadence
(preferrably both!) to actually implement the proposal and feed back
to the committee proposals to fix any broken parts of the proposal
based on your actual implementation experiences.
-mac
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