From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Sep 27 1999 - 08:58:55 PDT
Good morning:
Here are some more comments about draft 3:
1. Section 2.8 Attributes
Some examples terminate an attribute definition with a semicolon ';'.
This is not specified in the BNF fragment. This character is
not required no legal.
Examples on page 16 show this character.
I thought we were also going to allow an attribute of this form.
module foo;
// Attribute as part of the module.
(* my_data = "This is an extremenly long attribute.
In fact it spans multiple lines and may require something
to show that this is really legal.
Can I just do this, or must I include escapes "\" to
prefix newline characters?
" *)
...
endmodule
2. Section 3.2.2 'reg declarations'
I believe the proper statement should be 'Stuart Sutherland' instead
of 'Stu Sutherland'.
3. Section 3.3.2 'Vector net accessibility'
May we deprecate the optional standard of 'vectored' and 'scalared'?
4. Section 13.2.1 'Specifying libraries...' Page 187
The example library 'rtlLib' line is missing the '.' in "./*.v".
5. Section 13.3.1 'Basic configuration syntax' Page 188.
Are the '\' characters required in the "config_rule_statement"
definition? This would be out of charcter with existing verilog.
6. Section 13.3.1.1 'Design statement' page 188.
What is "lib.cell:view" We removed 'view's. Should it be
'lib.cell:config'?
Also, I believe there needs to be one mention that there may
be multiple top level modules - even though only one
'design' statement is allowed.
One question: If 'only one design statement is allowed'
does this preclude a command line switch to add additional
top level modules to the design statement list?
<p><p>Thanks for the time of everyone.
Adam Krolnik
Verification Mgr.
LSI Logic Inc.
Plano TX.
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:29 PDT
and
sponsored by Boyd Technology, Inc.