BTF Errata errors in Draft 3

From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Sat Oct 09 1999 - 11:09:47 PDT


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Cliff,
<p>I have gone through all the BTF errata passed by the 1364 WG to make
sure they
<br>are corrected in Draft 3. Most of them are corrected but not all of
them. Below is
<br>a list of the incorrectly implemented or missing BTF errata in Draft
3 plus a few more
<br>that I found along the way. All errata not in the list below are OK.
<br>
<ul>
<li>
<b>BE7</b> - The syntax for timing_check_condition in Syntax 15-14 is different
than in <br>
    A.7 on page 741.<br>
<BR></li>

<li>
<b>BE8</b> - The syntax for real number on page 793 is incorrect. The "1"
refers to note 1,<br>
    it should not be part of the syntax.<br>
<BR></li>

<li>
<b>BE18</b> - page 179 section 12.4 at the end of the second paragraph:
"See section ???"<br>
    should be "See section 10.2.1 and 10.3.1"<br>
    Figure 12-2 on page 181: move the second column an inch
to the right.<br>
The following text from BE18 is missing on page 182 after the example:<br>
<br>
<i> The name of a module or module instance is sufficient to identify
the module and its location in the hierarchy. A lower-level module can <br>
reference items in a module above it in the</i></li>

<br><i>hierarchy. For variables they can be referenced if the name of the
higher-level module or its instance name is known. For tasks, <br>
functions and named blocks, Verilog will look in the</i>
<br><i>enclosing module for the name, until it is found or until the root
of the hierarchy is reached. It will only search in higher enclosing modules <br>
for the name, not instances. The syntax for a</i>
<br><i>hierarchical reference is as follows:</i>
<br><i> </i>
<br><i> &lt;name_of_module_or_instance>.&lt;name_of_item></i>
<br><i> </i>
<br><i>There can be no spaces within the reference, except for escaped
identifiers embedded in the hierarchical name reference,. <br>
Example 12-11 demonstrates upward referencing. In this</i>
<br><i>example, there are four modules, mod_a, mod_b, mod_c and mod_d.
Each module contains an integer x. <br>
The highest level modules in this segment of a model hierarchy are mod_a
and</i>
<br><i>mod_d. There are two copies of module mod_b.x because both mod_a
and mod_d both instantiate mod_b.X. <br>
There are four copies of mod_c.x because each of the two copies of</i>
<br><i>mod_b.x instantiates mod_c.x twice. }</i>
<br><i> <br>
On page 183, the last line in the third paragraph of 12.5. The line should
be:</i><br>
<BR>
<br><i>a module boundary is encountered. {If the item is a variable, it
will stop at a module</i>
<br><i>boundary; if the item is a task, function, or named block it continues
to search higher-level modules until found.} <br>
The search {for variables} shall cross named block, task and function</i>
<br><i>boundaries but not module boundaries. <br>
<br>
</i>The following section of text is missing after the first paragraph
on page 184:
<br><br>
<i>If an identifier is referenced with a hierarchical name, the path can
start with an module name, instance name, task, function, <br>
or named block. The names will be searched first at the</i>
<br><i>current level, then in higher-level modules until found. Since both
module names and instance names can be used, <br>
precedence is given to instance names if there is a module named</i>
<br><i>the same as an instance name.</i><br>
<br>
<BR>
<li>
<b>BE24</b> - In the fourth paragraph of section 12.2.1 on page 170.
The second sentence should be: "When defparams are encountered in<br>
    multiple source files, e.g. found by library searching,
the defparam......<br>
<BR></li>

<li>
<b>BE31</b> - Syntax 6-1 on page 64. Last line of net_declaration syntax
should be:<br>
    list_of_net_decl_assignments. (decl typed dcl).<br>
<BR></li>

<li>
<b>BE39</b> - Last paragraph of section 10.2.1 on page 144. The reference
on the first line should be "(see 12.3.2 and 3.2.2)"<br>
<BR></li>

<li>
<b>BE41</b> - Syntax 9-4 on page 121 is not the same as in A.6. Syntax
9-6 is missing "attribute" see page 737.<br>
    Syntax 9-10 on page 131 should be "hierarchical_event_identifier".<br>
    Syntax 11-1 on page 151 is missing "hierarchical", see
page 738<br>
<BR></li>

<li>
<b>BE52</b> - Section 3.2.2 on page 18. The following sentence is missing:
" The default initialization <br>
    value for real and realtime reg datatypes shall be 0.0".
It should follow the sentence:<br>
    The default initialization value for a reg datatype......<br>
<BR></li>

<li>
<b>BE55</b> - This one doesn't seem to be implemented at all....<br>
    Replace the first paragraph in section 3.5 on page 21
with:<br>
<br>
<i>The syntax shown in Section 3.2 shall be used to declare nets and registers
explicitly. In the absence of an explicit declaration, <br>
an implicit net of default net type shall be assumed in the following circumstances:</i></li>
<i></i>
<p><br><i>- If an identifier is used in a port expression declaration,
then an implicit net of type wire shall be assumed, with the vector width
of <br>
the port expression declaration. See Section 12.3.2 for a discussion of
port expression declarations.</i><i></i>
<p><i>- If an identifier is used in the terminal list of a primitive instance
or a module instance, and that identifier has not been</i>
<br><i>explicitly declared previously in one of the declaration statements
of the instantiating module, then an implicit scalar net of <br>
default net type shall be assumed. <br>
<br>
</i>Section 12.3.2 on page 173: change the second word "port" to "port_expression"
.<br>
<br>
In section 12.3.2 on page 174. Chage the sentence "A port can be declared
in both a port declaration and a net or register declaration. <br>
    If a port is declared as a vector, the range specification
between the two declarations of a port shall be identical. " to:<br>
<br>
<i>A port_expression which is an identifier can be declared in both a port
declaration and a net or register declaration. A net or register <br>
declaration establishes the data type of the</i>
<br><i>internal net or register connected to the port. If no net or register
declaration is made for the port_expression identifier, <br>
then a default data type is assumed.</i><i></i>
<p><i>An explicit net or register declaration for an identifier which is
also used in a port_expression declares the specific data type <br>
and vector size of the port_expression. If the vector</i>
<br><i>range of a data type declaration differs from the vector range of
a port_expression declaration for the same identifier, <br>
the declaration of the net or register shall be used.</i><i></i>
<p><i>If there is no explicit net or register declaration for an identifier
used in a port_expression declaration, then an implicit net shall be assumed, <br>
with the vector width of the port_expression declaration. The implicit
net data type shall be wire, unless another default type has been directed. <br>
See Section 19.2 for a discussion of control of the type for implicitly</i>
<br><i>declared nets using the `default_nettype compiler directive. This
implicit net type shall be used for the internal net type when the rules <br>
for connecting dissimilar ports are applied.</i>
<br><i>These rules are discussed in Section 12.3.6 and Section 12.3.8. </i><br>
<br>
<BR>
<li>
<b>BE57</b> - Section 4.2.3.1 on page 51. Remove extra white space in "8*n
bits"<br>
<BR></li>

<li>
<b>BE59</b> - Sectoin 4.4.2 on page 55. Several typos in the example.<br>
    (ab) should be (a&amp;b)<br>
    emdmodule should be endmodule<br>
    ab in the text following the example should be a&amp;b
(two places)<br>
<BR></li>

<li>
<b>BE63</b> - Section 9.7.7 examples on page 134.<br>
    The comments under "repeat (-3)" and "repeat (a)" should
be moved to the right hand side of the page<br>
    to make the example easier to follow.<br>
<BR></li>

<li>
<b>BE71</b> - In A.4 page 734. Change "list_of_module_connections" to "list_of_port_connections"<br>
    In the example on page 174. Align all the comments under
the module declarations in one column<br>
    towards the right side of the page.<br>
<BR></li>

<li>
<b>BE74</b> - This one is not implemented in the BNF. Section A.8 page
741.<br>
    Replace all occurences of "multiple_concatenation" with
"replication".<br>
    Replace the definition of multiple_concatienation with
the definition of replication:<br>
    <tt>replication ::= {constant_expresson concatenation
}</tt><br>
<BR></li>

<li>
<b>BE82</b> - This is not implemented in the BNF section A.8 on page 743.<br>
    Replace "size" with "non_zero_size" in the syntax for
decimal, binary, octal and hex number.<br>
    Add the following syntax:<br>
<br>
non_zero_size ::=</li>

<br>
non_zero_unsigned_number
<p>non_zero_unsigned_number ::=
<br>
non_zero_decimal_digit { _ | decimal_digit}
<p>non_zero_decimal_digit ::=
<br>
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
<br>
<br>
<li>
<b>BE83</b> - The Note in section 9.2 on page 114.<br>
    The text is not correct, it should be:<br>
<br>
    <i>When the right-hadn side evaluates to fewer bits
than the left-hand side, then if the right-hand side<br>
    is signed (see Section 4.5), it shall be sign-extended
to the size of the left-hand side.</i><br>
<BR></li>

<li>
<b>BE84</b> - Section 3.12 page 32. In the third paragraph, add one white
space before the word "Once".<br>
    Section 12.3.4 on page 175. Add the following sentence:<br>
    "Once a port is connected by name, there shall not be
another named port connection for this port"<br>
<BR></li>

<li>
<b>BE86</b> - In Table 4-5 on page 39. Change "multiply" to "multiplied"
and<br>
    change "divide" to "divided"<br>
<BR></li>

<li>
<b>BE90</b> - Section 4.4.3 on page 55. Align the comments under simulator
output with the ones above.<br>
<BR></li>

<li>
<b>BE91</b> - Annex A page 742. The syntax for regl_value is missing "real_identifier"<br>
<BR></li>

<li>
Note 2 in the BNF section, page 746 need some meaningful text or should
be removed.<br>
<BR></li>

<li>
The "box" around Syntax 15-1, 15-2 through 15-12 on pages 224 to 237 are
missing.<br>
<BR></li>

<li>
Section 3.2.2 page 18. Typo in the middle of the first paragraph: "shall
be he unknown" should<br>
    be "shall be the unknown"<br>
<BR></li>

<li>
Example 1 and 2 on pages 158 and 159:<br>
    Align all the comments in one column towards the right
hand side of the page to make them easier to read.</li>
</ul>

<p>Regards,
<p>
Anders
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