From: Stuart Sutherland (stuart@sutherland.com)
Date: Tue Oct 12 1999 - 16:06:12 PDT
Anders,
Are escaped identifiers permitted as a macro name? I've never tried it,
and don't know what happens now.
Stu
At 11:14 AM 10/12/99, Anders Nordstrom wrote:
Hi,
I saw this post on comp.lang.verilog and I tried it with VCS.
If you have a dot (.) in the text_macro_name it is ignored.
The text in Section 19.3 in Draft 3 of the LRM does not preclude the use of
dot (.) in
the text_macro_name but the BNF does.
Proposal:
For clarification, add the following sentence at the end of the first
paragraph
of section 19.3.1 on page 314:
"The text macro name must be a legal identifier name"
The text in Syntax 19-2 and 19-3 are missing in Annex A. Propose to add them
in section A.9 on page 744.
Regards,
Anders
sundeep_chadha@my-deja.com wrote:
Hi,
I have a design that need to be tested at weird clock
frequencies/time periods ( like 10.1 ns, 13.3 ns etc.)
I have a section in the testbench that will generate
the above clocks based on the `defines that are passed to it.
It looks like this :
ection of the testbench
------------------------
`ifdef clock_10.1
......
generate clock 10.1 ns
......
`else
......
generate clock 13.3 ns
.......
`endif
The problem are two :
1. The simulator (verilog-XL) does not allow to pass on
the `defines in a file that can be compiled with the
testbench. eg: I can put these `defines in a file defines.v
and then run
verilog defines.v testbench.v
The defines.v has the line `define clock_10.1
The simulator gives a syntax error in the file defines.v in this case.
2. The simulator does not give any error while I pass
the `define on the command line instead of passing it
through a file. eg : If I compile like
verilog +define+clock_10.1 testbench.v
then there is no syntax error but the define is not
honoured. So in this case 13.3 clock is generated.
I suspect that the simulator takes the "." in the
`define as some hierarchical path and so gives a
syntax error in the case of defines.v but then why
case 2 passes without any syntax error ( the clock
is still not generated properly even then )
Can anybody help ?
Sundeep
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