From: Shalom Bresticker (r50386@email.sps.mot.com)
Date: Wed Oct 13 1999 - 00:10:46 PDT
Verilog-XL 2.6.38 treats it as follows:
1. If you write
`define clock_10.1
it treats it as though you wrote
`define clock_10 .1 // (space between 10 and .1)
2. If you use an escaped identifier
`define \clock_10.1
then it works.
3. The LRM is not quite clear on the term "identifier".
Section 2.7 on page 13 of Draft 3 says,
"An identifier shall be any sequence of letters, digits, dollar signs ($), and underscore characters (_)."
This is actually the definition of a "simple_identifier",
whereas in general an identifier may be either a "simple_identifier" or
an "escaped_identifier", defined in 2.7.1.
Shalom
Anders Nordstrom wrote:
>
> Hi,
>
> I saw this post on comp.lang.verilog and I tried it with VCS.
> If you have a dot (.) in the text_macro_name it is ignored.
>
> The text in Section 19.3 in Draft 3 of the LRM does not preclude the use of dot (.) in
> the text_macro_name but the BNF does.
>
> Proposal:
> For clarification, add the following sentence at the end of the first paragraph
> of section 19.3.1 on page 314:
> "The text macro name must be a legal identifier name"
>
> The text in Syntax 19-2 and 19-3 are missing in Annex A. Propose to add them
> in section A.9 on page 744.
>
> Regards,
>
> Anders
>
>
> sundeep_chadha@my-deja.com wrote:
>
> > Hi,
> >
> > I have a design that need to be tested at weird clock
> > frequencies/time periods ( like 10.1 ns, 13.3 ns etc.)
> >
> > I have a section in the testbench that will generate
> > the above clocks based on the `defines that are passed to it.
> > It looks like this :
> >
> > section of the testbench
> > ------------------------
> > `ifdef clock_10.1
> > ......
> > generate clock 10.1 ns
> > ......
> > `else
> > ......
> > generate clock 13.3 ns
> > .......
> > `endif
> >
> > The problem are two :
> > 1. The simulator (verilog-XL) does not allow to pass on
> > the `defines in a file that can be compiled with the
> > testbench. eg: I can put these `defines in a file defines.v
> > and then run
> >
> > verilog defines.v testbench.v
> > The defines.v has the line `define clock_10.1
> > The simulator gives a syntax error in the file defines.v in this case.
> >
> > 2. The simulator does not give any error while I pass
> > the `define on the command line instead of passing it
> > through a file. eg : If I compile like
> > verilog +define+clock_10.1 testbench.v
> > then there is no syntax error but the define is not
> > honoured. So in this case 13.3 clock is generated.
> >
> > I suspect that the simulator takes the "." in the
> > `define as some hierarchical path and so gives a
> > syntax error in the case of defines.v but then why
> > case 2 passes without any syntax error ( the clock
> > is still not generated properly even then )
> >
> > Can anybody help ?
> >
> > Sundeep
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> Anders Nordstrom <andersn@nortelnetworks.com>
> Manager OC-192 Data ASIC Development
> Nortel Networks Inc
> Dept 1V29
>
> Anders Nordstrom
> Manager OC-192 Data ASIC Development <andersn@nortelnetworks.com>
> Nortel Networks Inc HTML Mail
> Dept 1V29
> P.O. Box 3511 Station C Work: 613-763-9186
> Ottawa Netscape Conference Address
> Ontario Netscape Conference DLS Server
> K1Y 4H7
> Canada
> Additional Information:
> Last Name Nordstrom
> First Name Anders
> Version 2.1
--Shalom Bresticker
****************************************************************************** Shalom Bresticker email: shalom@msil.sps.mot.com Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268 P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444 http://www.motorola-semi.co.il/ ******************************************************************************
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:30 PDT
and
sponsored by Boyd Technology, Inc.