From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Wed Oct 13 1999 - 06:03:23 PDT
<x-html>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<body text="#000000" bgcolor="#FFFFFF" link="#0000FF" vlink="#FF0000" alink="#000088">
Stu,
<p>Escaped identifiers are not permitted in VCS so we could add the following
syntax
<br>to Syntax box 19-2:
<p><tt><i>text_macro_</i>identifier ::= simple_identifier</tt><tt></tt>
<p>Regards,
<p> Anders
<br>
<p>Stuart Sutherland wrote:
<blockquote TYPE=CITE>Anders,
<p>Are escaped identifiers permitted as a macro name? I've never
tried it,
<br>and don't know what happens now.
<p>Stu
<p>At 11:14 AM 10/12/99, Anders Nordstrom wrote:
<br>Hi,
<p>I saw this post on comp.lang.verilog and I tried it with VCS.
<br>If you have a dot (.) in the text_macro_name it is ignored.
<p>The text in Section 19.3 in Draft 3 of the LRM does not preclude the
use of
<br>dot (.) in
<br>the text_macro_name but the BNF does.
<p>Proposal:
<br>For clarification, add the following sentence at the end of the first
<br>paragraph
<br>of section 19.3.1 on page 314:
<br>"The text macro name must be a legal identifier name"
<p>The text in Syntax 19-2 and 19-3 are missing in Annex A. Propose to
add them
<br>in section A.9 on page 744.
<p>Regards,
<p> Anders
<br>
<p>sundeep_chadha@my-deja.com wrote:
<br>Hi,
<p>I have a design that need to be tested at weird clock
<br>frequencies/time periods ( like 10.1 ns, 13.3 ns etc.)
<p>I have a section in the testbench that will generate
<br>the above clocks based on the `defines that are passed to it.
<br>It looks like this :
<p>section of the testbench
<br>------------------------
<br>`ifdef clock_10.1
<br> ......
<br> generate clock 10.1 ns
<br> ......
<br>`else
<br> ......
<br> generate clock 13.3 ns
<br> .......
<br>`endif
<p>The problem are two :
<br>1. The simulator (verilog-XL) does not allow to pass on
<br>the `defines in a file that can be compiled with the
<br>testbench. eg: I can put these `defines in a file defines.v
<br>and then run
<p>verilog defines.v testbench.v
<br>The defines.v has the line `define clock_10.1
<br>The simulator gives a syntax error in the file defines.v in this case.
<p>2. The simulator does not give any error while I pass
<br>the `define on the command line instead of passing it
<br>through a file. eg : If I compile like
<br> verilog +define+clock_10.1 testbench.v
<br>then there is no syntax error but the define is not
<br>honoured. So in this case 13.3 clock is generated.
<p>I suspect that the simulator takes the "." in the
<br>`define as some hierarchical path and so gives a
<br>syntax error in the case of defines.v but then why
<br>case 2 passes without any syntax error ( the clock
<br>is still not generated properly even then )
<p>Can anybody help ?
<p>Sundeep
<p>Sent via Deja.com http://www.deja.com/>
<br>Before you buy.
<p>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
<br>Stuart Sutherland
Sutherland HDL Inc.
<br>stuart@sutherland.com
22805 SW 92nd Place
<br>phone: 503-692-0898
Tualatin, OR 97062</blockquote>
</body>
</html>
</x-html>
Attachment Converted: "C:\Documents and Settings\stefen\Application Data\Qualcomm\Eudora\andersn16.vcf"
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:53:30 PDT
and
sponsored by Boyd Technology, Inc.