From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Thu Oct 14 1999 - 07:22:13 PDT
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Cliff,
<p>I have reviewed B35 - PLA System Task Enhancement and B41 - `elsif
<br>and found a couple of errors in the LRM for both of them.
<br>
<p>(Draft 3 page 281, Syntax box 17-9)
<p>PROPOSED CHANGE:
<br>Remove the last line in the box (scalar_variables syntax)
<br>since it is not used in the input and output terms syntax any
<br>more. It was used in the 1995 LRM.
<br>
<p>(Draft 3 page 282, first example in section 17.5.2)
<p>WAS:
<br>An example of a nor plane system call is a follows:
<br><b>$async$nor$array</b> (mem,......
<p>PROPOSED CHANGE:
<br>An example of a nor plane system call is a follows:
<br><b>$async$nor$plane</b> (mem,......
<br>
<p>(Draft 3 page 316, section 19.4, second paragraph)
<p>WAS:
<br>If the `elsif directive exists (instead of the `else) the compiler
checks for the definition of the variable name.
<br>If the name exists the lines following the `elsif directive are included.
The `elsif directive is equivalent to the
<br>compiler directive sequence `elsif `ifdef ... `endif. This directive
does not need a corresponding `endif directive.
<br>This directive must be preceded by an `ifdef or `ifndef directive.
<p>PROPOSED CHANGE:
<br>If the <b>`</b>elsif<b> </b>directive exists (instead of the `else)
the compiler checks for the definition of the variable name.
<br>If the name exists the lines following the `elsif directive are included.
The `elsif directive is equivalent to
<br>the compiler directive sequence <font color="#FF0000">`else </font>`ifdef
... `endif. This directive does not need a corresponding `endif directive.
<br>This directive must be preceded by an `ifdef or `ifndef directive.
<br>
<p>(Draft 3 page 317, Syntax box 19-5)
<p>WAS:
<br>[ <b>`else</b> another_group_of_lines <b>`endif </b>]
<p>PROPOSED CHANGE:
<br>Change both instances of the line above to:
<br>[ <b>`else</b> another_group_of_lines<b> </b>]
<br>
<p>(Draft 3 page 317, section 19.4, first paragraph under syntax box 19-5)
<p>WAS:
<br>The <tt>text_macro_name</tt> is a Verilog HDL identifier.
<p>PROPOSED CHANGE:
<br>The <tt>text_macro_name</tt> is a Verilog HDL simple_identifier.
<br>
<p>(Draft 3 page 318, section 19.4, after example 2)
<p>PROPOSED CHANGE:
<br>Example 3 in the passed B41 proposal is missing on page 318.
<br>Add the following text after Example 2 on page 318:
<p>Example 3 - The following example shows usage of chained nested conditional
compilation directives.
<p> module
test;
<br>
`ifdef first_block
<br>
`ifndef second_nest
<br>
initial $display("first_block defined.");
<br>
`else
<br>
initial $display("first_block and second_nest defined.");
<br>
`endif
<br>
`elsif second_block
<br>
initial $display("second_block defined, first_block not defined.");
<br>
`else
<br>
`ifndef last_result
<br>
initial $display("first_block, second_block, last_result not defined.");
<br>
`elsif real_last
<br>
initial $display("first_block, second_block not defined; last_result and
real_last defined.");
<br>
`else
<br>
initial $display("Only last_result defined!");
<br>
`endif
<br>
`endif
<br>
endmodule
<br>
<p>(Draft 3 page 811, index)
<p>PROPOSED CHANGE:
<br>Add <b>`elsif</b> to the index on page 811
<br>
<br>
<br>
<p>Regards,
<p>
Anders
<br>
<br>
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