[Fwd: Question of `undef]

From: Shalom Bresticker (r50386@email.sps.mot.com)
Date: Tue Nov 09 1999 - 00:59:13 PST

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I found the following old mail.
<BR>What is the correct answer ?

Shalom
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Message-ID: <md5:22D8530FCAD0E7638D7065344245E450>
Newsgroups: comp.lang.verilog
Subject: Question of `undef
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<p>To Verilog Expert

I get a question of `undef directive in IEEE 1364.

In LRM 16.3.2 (page 222), the syntax of `undef is

  undefine_compiler_directive ::= `undef text_macro_name

  text_macro_name ::= identify [ ( list_of_formal_arguments ) ]

My question is :

  Is the following verilog code legal ?

<p> `define max(a,b) ((a) > (b))? (a) : (b)

  `undef max(a,b)

or only use "`undef max"

Any answer will be appreciate. Thanks.

<p> 

-- 

---- Ta-Yung Liu

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