Re: Proposed changes to Verilog Generate

From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Nov 18 1999 - 15:16:00 PST


Good afternoon:

Regarding Steve's mail proposing:

  PROPOSED CHANGE:
  Require a named generate_block for generate loops to disambiguate
  generated hierarchical names. The same change needs to be made in
  the BNF. Format with bold as usual.

It is unfortunate to require names for block when the common case
is to not need a name. Is there more weight to this request than
to visually disambiguate nested loop name components?

>From the example provided:

  // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1

We may need to make a small statement indicating that the
period (.) does not always imply a scope change. I can
see some tool missing this point and screwing up a name.

E.g.

generate
  for(...)
   begin :b
    wire me;
 ...
endgenerate

<p>always @(b[2].me) // This is not in some other instantiation!

<p> Adam Krolnik
   Verification Mgr.
   LSI Logic, INC.
   Plano TX. 75074



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